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Newbie
Newbie
321 Views
Registered: ‎09-11-2019

How to tell the vivado not to use particular region in FPGA

Hi ,

Is tere any constraint ,so that my logic will not placed any particular region of the FPGA. 

We have the constraints to keep the logic in particular region,like this way is there any constraint not to use some region of the FPGA.

 

Thanks in adavance,

Sai

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2 Replies
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Moderator
Moderator
306 Views
Registered: ‎11-04-2010

Re: How to tell the vivado not to use particular region in FPGA

Hi, @sai777 ,

Do you mean all the logic cannot be placed in the specific region?

You can try to set the prohibit property to avoid logic placing.

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Moderator
Moderator
276 Views
Registered: ‎11-04-2010

Re: How to tell the vivado not to use particular region in FPGA

Hi, @sai777 ,

Another method for you to try:

1. Create an empty pblock which contains the region you don't want to place any logic.
2. Set the pblock as Placement excluded to avoid the logic enter the specific region.

Example constraints:

create_pblock pblock_1
resize_pblock pblock_1 -add CLOCKREGION_X1Y3:CLOCKREGION_X1Y3
set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_1]

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