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jsobas
Visitor
Visitor
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Registered: ‎11-02-2020

How use Save(S or SAVE)constraint ?

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Hello,

I want to integrate a Ring Oscillator (9 Buffers+1 inverser) on a XC6LX16 FPGA. I work with ISE 14.7 interface.

I have the folowing error message during the "MAP" :

ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx

 

I have searched in the forum and the Xilinx documentation about this error and I understand that I have to add a 'SAVE' attribute in my VHDL design. But I don't understand how integrate the SAVE attributes in my VHDL code ?

Any help is WELCOME

Here after the source code of my Ring Oscillator (VHDL) :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity RO_Buf_9 is
Port ( F_RO_9_Buf : out STD_LOGIC);
end RO_Buf_9;

architecture Behavioral of RO_Buf_9 is

signal E0 : STD_LOGIC;
signal E1 : STD_LOGIC;
signal E2 : STD_LOGIC;
signal E3 : STD_LOGIC;
signal E4 : STD_LOGIC;
signal E5 : STD_LOGIC;
signal E6 : STD_LOGIC;
signal E7 : STD_LOGIC;
signal E8 : STD_LOGIC;
signal E9 : STD_LOGIC;


begin

--Inverser
E0 <= not E9;

--9 Buffers
E1 <= E0;
E2 <= E1;
E3 <= E2;
E4 <= E3;
E5 <= E4;
E6 <= E5;
E7 <= E6;
E8 <= E7;
E9 <= E8;

--Output
F_RO_9_BUF <= E9;

end Behavioral;

Thanks

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amaccre
Moderator
Moderator
283 Views
Registered: ‎04-24-2013

Hi @jsobas ,

Have a look at the Save Net Flag section of UG625 Xilnx Constraint for the ISE syntax.

Best of luck trying to implement a ring oscillator on an FPGA, you may find the following of use: https://www.xilinx.com/support/documentation/application_notes/xapp872.pdf.

Best Regards
Aidan

 

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2 Replies
amaccre
Moderator
Moderator
284 Views
Registered: ‎04-24-2013

Hi @jsobas ,

Have a look at the Save Net Flag section of UG625 Xilnx Constraint for the ISE syntax.

Best of luck trying to implement a ring oscillator on an FPGA, you may find the following of use: https://www.xilinx.com/support/documentation/application_notes/xapp872.pdf.

Best Regards
Aidan

 

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Give Kudos to a post which you think is helpful and may help other users
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jsobas
Visitor
Visitor
257 Views
Registered: ‎11-02-2020

Thanks for the answer !

I put in attachment the .VHD that I create for Ring Oscillator with inverser ==> It works very WELL !!

have a good day !

 

 

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