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Visitor joleen.hind
Visitor
506 Views
Registered: ‎01-16-2019

IBUFDS_DIFF_OUT_IBUFDISABLE implementation failure

I am trying  to use the IBUFDISABLE of the IBUFDS_DIF_OUT_IBUFDSABLE in an Artix 7, Vivado 2017.4.  I have the pin connected to internal logic thru the power_down signal, and I get a conflicting error during implementation:

[Constraints 18-608] We cannot route the nets within the site IOB_X1Y104. Reason: Conflicting nets for physical connection IBUFDISABLE_SEL_OUT driven by M6.IBUFDISABLE_SEL.OUT: 1: GROUND, 2: bbif_if_i1/ad9361_bbif_if_i/ad9361_if_rx_inst/ad9361_if_rx_dpa_inst/IBUFDS_inst_i_1__0_n_0

 

 

What might be wrong? UG471 does not say anything about conflicts or restrictions on the pin or IOSTANDARD .  The HW has external termination, so the internal termination must be set to FALSE.   I confirmed after synthesis the internal logic for the power_down signal connected to IBUFDISABLE is as expected.

Here is the instantiation ( I used the template from Vivado):

 

IBUFDS_DIFF_OUT_IBUFDISABLE #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS_25"), // Specify the input I/O standard
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
) IBUFDS_inst_rxd (
.O(rxdp),
.OB(rxdn),
.I(rxd_p),
.IB(rxd_n),
.IBUFDISABLE(power_down) // Buffer disable input, high=disable
);

 

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5 Replies
Xilinx Employee
Xilinx Employee
468 Views
Registered: ‎01-30-2019

Re: IBUFDS_DIFF_OUT_IBUFDISABLE implementation failure

@joleen.hind 

Can you show us the schematic of the design?

or RTL files and XDC files necessary to reproduce the design or test case?

--Suraj

 

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Xilinx Employee
Xilinx Employee
457 Views
Registered: ‎02-27-2019

回复: IBUFDS_DIFF_OUT_IBUFDISABLE implementation failure

Hi @joleen.hind ,

Because I didn't get your source files, so I tested the instantiation which you posted in my design. The instantiation is fine.

xc7a200tffg1156-2    vivado2017.4

Below is my source file ,you can have a try . Hope it can help you.

top

module forums(
input clk,
input enable,
input rxd_p,
input rxd_n,
output rxp,
output rxn
    );
    IBUFDS_DIFF_OUT_IBUFDISABLE #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS_25"), // Specify the input I/O standard
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
) IBUFDS_inst_rxd (
.O(rxdp),
.OB(rxdn),
.I(rxd_p),
.IB(rxd_n),
.IBUFDISABLE(power_down) // Buffer disable input, high=disable
);

reg power_down;
reg rxp,rxn;
always@(posedge clk)begin
power_down<=enable;
rxp<=rxdp;
rxn<=rxdn;
end

endmodule

XDC file

set_property IOSTANDARD LVCMOS25 [get_ports clk]
set_property IOSTANDARD LVCMOS25 [get_ports enable]
set_property IOSTANDARD LVCMOS25 [get_ports rxn]
set_property IOSTANDARD LVCMOS25 [get_ports rxp]
set_property PACKAGE_PIN AD11 [get_ports enable]
set_property PACKAGE_PIN AF9 [get_ports rxd_p]
set_property PACKAGE_PIN AF8 [get_ports rxd_n]
set_property PACKAGE_PIN AG9 [get_ports rxn]
set_property PACKAGE_PIN AH9 [get_ports rxp]
set_property PACKAGE_PIN AG6 [get_ports clk]

 

 

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Visitor joleen.hind
Visitor
448 Views
Registered: ‎01-16-2019

回复: IBUFDS_DIFF_OUT_IBUFDISABLE implementation failure

I will not be able to share the RTL in a public forum.  This design works with IBUFDS_DIFF_OUT and has been so for several years. But now there is a need to have a disable mode on the inputs, so that is the only change I am making it to instantiate the IBUFDS_DIFF_OUT with the IBUFDISABLE option tied to some internal logic.  

Here is the schematic after synthesis, failed to implement in 2017.4, but implements with same RTL in 2018.1.  However my design fails timing in 2018.1 wihtout any build setting changes or RTL changes.  For IP reasons, the desire is to stay in 2017.4 version.  Is there a known issue that was fixed in 2018.1 for this?  Is there a 2017.4 workaround?

 

 

Capture.JPG

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Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎02-27-2019

回复: IBUFDS_DIFF_OUT_IBUFDISABLE implementation failure

Hi @joleen.hind ,

Different Vivado version maybe performs different timing report as its algorithm has changed . Even with the same vivado version , the timing report is different when you choose different implementation strategy.

Could you install  Vivado 2017.4 update 1  and have a try? 

Capture.PNG

 

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Visitor joleen.hind
Visitor
416 Views
Registered: ‎01-16-2019

回复: IBUFDS_DIFF_OUT_IBUFDISABLE implementation failure

The specific issue with 2017.4 is not a timing issue, it is a failure to implement due to trying to use the IBUFDS_DIFF_OUT_IBUFDISABLE instantiation. I see nothing in the release notes that suggest 2017.4.1 fixes this. Our flow uses a server installation shared across many sites so I cannot get this installed in a timely manner.  Is there a way of patching it in without a full install, in a Linux environment so I can prove it works before having to go thru a full tool reinstall?   

If there isn't a method, I will have to open a service request against the tool.

Regards,

Joleen

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