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tim_severance
Scholar
Scholar
6,192 Views
Registered: ‎03-03-2017

IO Standard default when XDC clearly defines location and io standard

Hi,

   I am using Vivado 2016.4 for a design on the Kintex 7 and am having an issue where bitstream generation fails because it thinks many pins are "default" IO standard, whereas my XDC file does indeed contain IO standard and locations for the pins mentioned.

   Is there a way I can see some log file where it shows that indeed my XDC file was parsed, and whether the pins that are an issue gave some kind of error during the XDC parsing?

Thanks.

Tim

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10 Replies
markintosh.dl
Observer
Observer
6,190 Views
Registered: ‎02-29-2016

Hi @tim_severance, you should be able to see all the info, warnings, errors in the vivado.log file (in case you are running in batch mode). If you are running in Gui mode you have the messages tab,

Regards 

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tim_severance
Scholar
Scholar
6,178 Views
Registered: ‎03-03-2017

@markintosh.dl,

   I am running in GUI mode and see the messages tab, but these messages are not always showing all the info and looking at a raw log file is preferable.    Do you know if the Vivado.log is generated in GUI mode as well?

Thanks.  

Tim

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markintosh.dl
Observer
Observer
6,176 Views
Registered: ‎02-29-2016

Hi @tim_severance, it should be generated at the same level of hierarchy as your project. I always get it as vivado.log and I don't recall having to change any settings for that. Windows search/linux find might help you find it...
Regards

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tim_severance
Scholar
Scholar
6,171 Views
Registered: ‎03-03-2017

@markintosh.dl,

   I found the runme.log in the impl_1 folder to contain what I was looking for, and indeed it helped me determine what my problem was.

Thanks!

Tim

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avrumw
Guide
Guide
6,166 Views
Registered: ‎01-23-2009

The Vivado.log is generated, but it is in a weird place.

 

However, the actual processing done by Vivado in project mode doesn't go there - it goes in the individual log files for the processes.

 

In the GUI, in the bottom tab, click on "Log". Then when there there is another tab showing Synthesis, Implementation and Simulation. Look at Implementation - the full log should be there.

 

You can also find it in the project directory

 

<project>/<project>.runs/impl_1/runme.log

 

Avrum

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florentw
Moderator
Moderator
6,147 Views
Registered: ‎11-09-2015

Hi @avrumw,

 

The Vivado.log is generated, but it is in a weird place

-> This is not really a weird place where you know. It is generated in the directory from where you start vivado. To find this directory, just type pwd in the tcl console to know what is the directory. I usually use the cmd line to start vivado, even on windows. This way I know where the vivado.log and vivado.jou files are located.

Some of my colleagues start vivado using the icons but using vivado tcl console (tcl mode). This way they can cd the directory they want before starting the gui (start_gui)

 

If you are starting vivado directly from the desktop icon, to know or change the directory from which vivado is started, just right-click on the icon and click properties. The directory is the one in "Start in":

vivado.JPG

 

By default this is in %APPDATA%\Xilinx\Vivado but I always change it

 

@tim_severance,

You might remember this folder if you experience a crash in vivado because we (Xilinx Technical Support) need some file generated to this location when/if the tool crash (file .err + .log and .jou)

 

With that say, to know investigate the synthesis and implementation results I usually prefer the runme.log file in synth_1 and impl_1 as they contain only the information for the run (while vivado.log contains the information for all the session).

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tonykaravidas
Adventurer
Adventurer
6,095 Views
Registered: ‎02-04-2008

Tim, what was the problem? 

I'm having the same issue (posted about it in a different thread) where i have a pin defined in my XDC file, yet the tool says the default I/O Standard for that pin is something else:

 

ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 14. For example, the following two ports in this bank have conflicting VCCOs:  MCLK3 (LVCMOS18, requiring VCCO=1.800) and SDTO8 (LVCMOS33, requiring VCCO=3.300)

 

I've burned at least 30 minutes trying to fix this.

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hpoetzl
Voyager
Voyager
6,040 Views
Registered: ‎06-24-2013

Without detailed knowledge of your design, I'd say you have configured (explicitly or implicitly) two different I/O standards (LVCMOS18 and LVCMOS33) on the same bank (14) which is not physically possible.

 

Most likely one is explicitly set via some constraint (.xdc file) and the other one is a default.

 

Make sure to use only compatible standards on the same bank.

 

Hope that helps,

Herbert

-------------- Yes, I do this for fun!
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florentw
Moderator
Moderator
5,984 Views
Registered: ‎11-09-2015

Hi @tonykaravidas,

 

Or you could have also constraint from an IP.

 

You can check all the constraints applied to a design with the command write_xdc.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
akhan28
Newbie
Newbie
1,362 Views
Registered: ‎11-23-2019

I'm using vivado 2019.1 and it turns out in my .vhd I had "LEDS" and in my .xdc file I typed "LEDs".

I used to think vivado in vivado software upper case and lower case are considered same.

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