04-07-2016 02:20 AM
I have an IP module with associated constraint file. The constraint file has multipath and delay constraints in it which are based on clocks applied to the IP. The IP is instantiated inside a processor system block diagram and connected to the processors output clocks. When I run implementation the Vivado generated tcl build script puts all the processor system block diagram constraint files PROCESSING_ORDER properties to EARLY, the design then fails timing as my IP constraints cannot ‘get_clocks’ as the ‘Processor_System_Processing_System7_0.xdc’ (set to EARLY too) gets sourced after my IP constraint file (which is also EARLY) and the clocks have not been defined.
If I use the ‘IP Sources’ tab I can navigate to the IP constraint file and set the PROCESSING_ORDER to NORAML and everything builds as expected and meets timing; however, if I reset the project this information is lost as the generated output products are deleted. The PROCESSING_ORDER will then revert back to EARLY when the output products are regenerated.
Setting the PROCESSING_ORDER of the constraint file in the IP project does not seem to be communicated when packaging the project (I feel it only has scope in the IP project).
I then proceeded to write the below script:
set_property PROCESSING_ORDER NORMAL [get_files AXI_Video_Ethernet_Interface.xdc] puts -nonewline "AXI_Video_Ethernet_Interface.xdc processing order: " puts [get_property PROCESSING_ORDER [get_files AXI_Video_Ethernet_Interface.xdc]]
The last two lines are included for verification.
Including the tcl script in Implementation with PROCESSING_ORDER of EARLY fails as I believe the processing order has already been defined in the implementation build script. The processing order would be changed but it is after the point of interest.
The method I thought would work was to include the script in Synthesis so the IP’s PROCESSING_ORDER was set ready for implantation. The synthesis log indeed reported that the order had changed to NORMAL (via scripts verification output) but on reviewing the Vivado generated implementation build script the IP constraint file was again being set to EARLY.
I do not believe I can use the tcl.pre hooks easily due to the way they work so I have run out of ideas.
Can anyone suggest how to get an IP module’s constraint file PROCESSING_ORDER set to NORMAL/LATE automatically (probably via a script) or have a manual operation survive beyond a project reset?
09-20-2016 03:49 AM
I have the same problem, using 2015.4.
According to me, the PROCESSING_ORDER values are not preserved in
the component.xml file (using the IP Package editor).
Which version are you using ?
Did you find any workaround meanwhile ?