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Visitor dkelleystl
Visitor
5,223 Views
Registered: ‎03-29-2009

ISE 10.1.03 Map ignoring region constraints in Virtex5

I have a Virtex LX50T design that uses 19 global clocks.  I am trying to ensure that one of those clocks has access to the entire FPGA.  In previous MAP runs, the mapper automatically did this.  However, when I reduced the amount of logic on that clock domain it started restricting the logic to a smaller portion of the FPGA.  I know this is an attempt to limit the number of global clocks in a region to 10, but previous runs were able to give this global buffer access to the whole part.

 

I tried assigning this clock to all of the FPGA regions by copying into my UCF the clock constraints listed in the MAP file from the previous run (the one that gave this clock access to the whole FPGA) However, MAP ignores these constraints when it make its region assignments.

 

How do I get MAP to follow the clock area constraint to give this clock access to the whole FPGA?

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Xilinx Employee
Xilinx Employee
5,200 Views
Registered: ‎11-28-2007

Re: ISE 10.1.03 Map ignoring region constraints in Virtex5

The way how constraints work is that as long as the tool doesn't do things outside the constraints, then the constraints are met. e.g. if you constrain a clock to use 10 clock regions and the tool places logic driven by the clock in 5 of the specificed clock regions,  it's meeting the requirment. If you see clock congestion problem in a particular clock region, you can constraint other clocks away from that clock region so the clock you're interested can go into the clock region.

 

e.g. say if you don't want clock "clk1" to go to clock region X0Y1,  you can add area group constraint on the clock group to any clock regions other than clock region X0Y1:

 

AREA_GROUP "CLKAG_clk1" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y2;

 

Cheers,

Jim

Cheers,
Jim
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