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abdul_syed
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Registered: ‎04-14-2018

Implement Design Error on Spartan 6 using Xilinx ISE 14.7: Constraint File Error

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Hello, 

 

I have currently purchased Nexys 3 Spartan-6 FPGA Trainer Board and trying to implement a simple logic (2 inputs and 1 output) on this evaluation board. 

 

I am new to Xilinx ISE 14.7 on Windows 10 Operating System (Oracle Virtual Machine). I have created the following constraint file (.ucf) for my circuit (see below); 

 

NET "SW<0>" input_A LOC = "T10";
NET "SW<0>" input_A IOSTANDARD = "LVCMOS33";
NET "SW<1>" input_B LOC = "T9"; 
NET "SW<1>" input_B IOSTANDARD = "LVCMOS33";
NET "LED<0>" output_C LOC = "U16";
NET "LED<0>" output_C IOSTANDARD = "LVCMOS33";

 

I currently trying to implement a simple logic circuit with two inputs and one output. The tool has managed to successfully Synthesize but when I click and try to run the 'Implement Design' the tool states it 'Process "Translate" failed'. When I check the 'Error' tab the following error are stated;

 

ERROR:ConstraintSystem:300 - In file: constraints.ucf(1): Syntax error.  Ensure
   that the previous constraint specification was terminated with ';'.
ERROR:ConstraintSystem:300 - In file: constraints.ucf(2): Syntax error.  Ensure
   that the previous constraint specification was terminated with ';'.
ERROR:ConstraintSystem:300 - In file: constraints.ucf(3): Syntax error.  Ensure
   that the previous constraint specification was terminated with ';'.
ERROR:ConstraintSystem:300 - In file: constraints.ucf(4): Syntax error.  Ensure
   that the previous constraint specification was terminated with ';'.
ERROR:ConstraintSystem:300 - In file: constraints.ucf(5): Syntax error.  Ensure
   that the previous constraint specification was terminated with ';'.
ERROR:ConstraintSystem:300 - In file: constraints.ucf(6): Syntax error.  Ensure
   that the previous constraint specification was terminated with ';'.   

 

If I comment the constraint file with then it successfully completes the implement design. 

 

Please can you kindly assist me in solving this issue. 

 

 

error constraint.JPG
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hongh
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1,170 Views
Registered: ‎11-04-2010

Hi, @abdul_syed ,

Please confirm that only one net name(port name) follow "NET" in your UCF.

Example port name "input clk_p", "input reset", "output [7:0] counter_out":

NET "clk_p"  LOC = AD12;
NET "reset" LOC = AB7;
NET "counter_out[0]" LOC = AB8;

 

 

 

 

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hongh
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1,171 Views
Registered: ‎11-04-2010

Hi, @abdul_syed ,

Please confirm that only one net name(port name) follow "NET" in your UCF.

Example port name "input clk_p", "input reset", "output [7:0] counter_out":

NET "clk_p"  LOC = AD12;
NET "reset" LOC = AB7;
NET "counter_out[0]" LOC = AB8;

 

 

 

 

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abdul_syed
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Registered: ‎04-14-2018

Hi @hongh

Many thanks for your suggestion. I have implemented the design successfully without any errors by following your suggestion. 

The only problem I now facing is the VM Oracle doesn't recognize the USB connection to the evaluation board. See the attached screenshot.

 

Please can you advise me how I can configure the USB on the VM Oracle so that it recognize the USB connection. 

 

Many thanks

 

Error iMPACT screenshot.JPG
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hongh
Moderator
Moderator
1,094 Views
Registered: ‎11-04-2010

Hi, @abdul_syed ,

Since the error in Translation is resolved, please close the current thread and create a new topic in Configuration board for your new query. The configuration expert will continue to help you.

Thank you for your cooperation and understanding.

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