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Dra92
Visitor
Visitor
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Registered: ‎08-18-2020

Implementing FDPE flip flop

Hi everyone
I want to implement a FLIP FLOP (FDPE) to use its PRE port in one CLB. Unfortunately, when implemented, it changes to four different parts (FD, LD, FDP, LUT3). The other problem is not to be able to implement them in one CLB. Does someone know the reason for this?

I use Spartan 6 in ISE 14.7.

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

show us your code and we might be able to help.

Why are you trying to make a FDPE ?

You might need to understand that the tools take your abstracted description, and fit it into the device you specify to meet the timing constraints you set.

There are ways to force the use of a specific "part" of the FPGA ,
but in 40 years I have very very very rarely needed to do this,
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