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Visitor
Visitor
3,279 Views
Registered: ‎01-23-2013

Instantiate hard macro with antenna nets in FPGA editor

hi,

 

I want to insert special hard macro in my design. In this hard macro there are slices, whose inputs are not connected/routed, while their ouputs are manully routed into the switching matrix adjacent to them. These wires from slice output to switching matrix become antenna nets, as they have only source but no sink.

 

When I instantiate this kind of hard macro in vhdl and run synthesis/par, MAP always trims the hard macro away because the hard macro is not connected to any other part of the design. I have tried constraints like SAVE and KEEP, but no success.

 

So I tried FPGA editor to instantiate the hard macro manually ("Add Hard Macro Instance"). I first selected exactly the slice that is defined as the anchor in the hard macro, then chose Edit -> Add Hard Macro Instance, and gave the nmc filename. But FPGA editor simply was not able to place it. In the console it showed:

WARNING:FPGAEditor:696 - Cannot place hard macro "test" at site "SLICE_X56Y92" -- The route patterns of internal networks cannot be replicated.
WARNING:FPGAEditor:629 - Cannot place hard macro "test" at site "SLICE_X56Y92"
Added macro "test".

 I've uploaded the hard macro of the simplest case. It has two slice and only one antenna net.

 

Has anyone ideas? Thanks in advance

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2 Replies
Scholar
Scholar
3,271 Views
Registered: ‎02-27-2008

Why?

 

This is not a 'supported flow' so why would (anyone) need to do this?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar
Scholar
3,264 Views
Registered: ‎07-01-2008

I've never heard of a hard macro being trimmed. Map should just treat it like a black box and pass it through.

 

The hard macro flow is still supported but is only maintained to allow for work arounds to support confugurations that can't otherwise be pushed though map. It is most commonly used for unusual IO configurations that Map/Pack can't handle. There are a lot of issues with hard macros that won't be addressed.

 

There is no support in the ISE tools for partially routed nets. The new Vivado tools do support this however. You can define partial routes using Directed Routing constraints at the driver and/or load and the automatic routing will fill in the gaps.

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