cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
RobinKao
Newbie
Newbie
159 Views
Registered: ‎04-01-2021

Integrate submodule netlist into orhter project

Xilinx version: 2019

--------------------------------

Purpose : 

I want to save sub-module netlist and P&R information, and then integrate it into other project.

Q1:

I using write_verilog and add_cells_to_pblock command to get sub-module .edn and stub file at implementation stage.

But the sub-module port name and port numbers is complete different. It's hard to integrate to other project.

Do I need to keep sub-module boundary and re-synthesis and re-implementation again?

Q2:

When I write out sub-module .edn file with add_cells_to_pblock command at implementation stage. Does the .edn file contain 

place & route info and the info could carried into other project? 

Q3:

Do I need using OOC synthesis mode?

0 Kudos
0 Replies