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tarinip
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Registered: ‎02-02-2017

Interfacing OV7670 with Zedboard

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I am trying to interface ov7670 camera with zedboard .I have used hamsters code for that . But while synthesis and implementaion getting large amount of critical warning Is it safe to Ignore?My bitstream is not getting generated its showing error in that also .I am atttaching whatever i have done.

Please help.

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tarinip
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Observer
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Registered: ‎02-02-2017

Thanks for replying.I have seen that already and did what they said .Bitstream is getting generated but when i am doing program fpga It is getting programmed but its not showing output 

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tarinip
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Registered: ‎02-02-2017

 I am  getting these critical warning 

[Common 17-55] 'set_property' expects at least one object. ["C:/Users/admin/hoja/project_1/project_1.srcs/constrs_1/imports/hoja/zedboard.xdc":1]

Like this 40 warning

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 46 out of 46 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: vga_red[3:0], vga_green[3:0], vga_blue[3:0], frame_addr[18:0], frame_pixel[11:0], clk25, vga_hsync, vga_vsync.

Like this 2.

Is it safe to ignore this?

please help

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nupurs
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Registered: ‎06-24-2015

@tarinip,

 

Please see this AR : https://www.xilinx.com/support/answers/56354.html 

Thanks,
Nupur
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tarinip
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Registered: ‎02-02-2017

Thanks for replying.I have seen that already and did what they said .Bitstream is getting generated but when i am doing program fpga It is getting programmed but its not showing output 

View solution in original post

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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

This is always better to know what you are doing. So you should check what are the correct IO standard to assign for every IO and define it in the xdc file.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tarinip
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Thanks for reply.I think my xdc file has correct IO standard for ever IO.Can you please go through it

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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

If you could send the vivado.log file it could give more information of what is wrong.

 

But yes the xdc looks fine

 

Regards,

 

Florent


Florent
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tarinip
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Registered: ‎02-02-2017

Hello Florent,

Thanks for replying.I am attaching my log file

 

 

Regards

Tarini 

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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

That is weird. It seems that your xdc file is not read... Could you check if you have the correct file in vivado (in the constraint sources, is it the one marked target?)

 

Regards,

 

Florent


Florent
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tarinip
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Registered: ‎02-02-2017

Hello @florent

Thanks for replying. While generating the bitstream i was getting following error

DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 46 out of 46 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: vga_red[3:0], vga_green[3:0], vga_blue[3:0], frame_addr[18:0], frame_pixel[11:0], clk25, vga_hsync, vga_vsync.

Like this 2.

as suggested in https://www.xilinx.com/support/answers/56354.html

I did this part as my synthesis and implementation were run without error though they had critical errors

3. If you just need to generate the bit file from the existing completed Implementation run and temporarily ignore those unconstrained I/Os, use this solution

 After doing this Xdc file doesnt remain the constraint target.

What should I do?

Regards

 

Tarini

 

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tarinip
Observer
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Registered: ‎02-02-2017

This is the screenshot

target.PNG
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tarinip
Observer
Observer
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Registered: ‎02-02-2017

Hello @florent,

I have solved  my previous errors and I have generated  my Bitstream is generated but  when  I program using  hardware target . It's getting programmed but  not showing  the output. Instead there  are 2 warnings the debug hub vote was  not detected  at user scan chain 1or 3

1) Make sure clock  connected  to debug hub core  is in free  running clock and is active OR

2)manually launch hw_server  one

I have gone through the  https://www.xilinx.com/support/answers/64764.html

But still not getting output

 Thank you

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tarinip
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Registered: ‎02-02-2017

FPGA is programmed. To see whether the code is working, an LED0 is made to glow and after programming the FPGA, it is glowing. But the camera output is still not visible. These are the warnings that we are getting. Could you go through it? 

 

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].

 

Thanks

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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

Did you add an ILA in your design? If you need to start the zynq PS (in vivado run an application). Same thing if you are using a clock from the zynq

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tarinip
Observer
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Registered: ‎02-02-2017

Hello @florentw

 

Thanks for replying.

 

At first I didn't have port mapping of Block memory generator. Now that I have it, it is giving the following error. Could you please go through it ? 

 

If this port mapping is done properly then I'll be able to work on adding ILA in the design as you have suggested.

 

Thanks in advance .

error1.png
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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

You are missing the connent of blk_mem_gen. You need to add the sources corresponding.

 

Regards,

 

Florent


Florent
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tarinip
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Registered: ‎02-02-2017

Hello @florentw 

 I tried to do that but still showing error .Could you please suggest how to do that?

 

 

Thanks 

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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

Well... "Add sources"... This is the only thing I see to do that.

 

Regards,

 

Florent


Florent
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tarinip
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Hello @florentw,

I tried that only but its not going 

 

 

Thank you

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florentw
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Registered: ‎11-09-2015

@tarinip,

 

What is your input format? xci, vhd, v?

 

You have a block design, what is inside?

 

Regards,

 

Florent


Florent
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tarinip
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Registered: ‎02-02-2017

Hello @florentw

Its vhd file .Could please go through the screenshot

 

 

Thank you

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tarinip
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Hello

screenshot

bd.png
source.png
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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

I think the blk_mem_gen and xilinx_frame_buffer are xilinx IPs you need to generate (or add the xci files). Do you have any information? Where did you get the sources?

 

Thanks,

 

Florent


Florent
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tarinip
Observer
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Hello @florentw

 

Frame buffer is not xilinx ip but Block memory generator is the xilinx IP .I got sources from 

http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670

 

 

 

Thank you

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florentw
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Registered: ‎11-09-2015

HI @tarinip,

 

The sources are for ISE not for Vivado. That is probably why you have issues in your project.

 

The best way to start is maybe to start with ISE and when it is working then move to Vivado.

 

Or search for another example project made with vivado:

https://lauri.võsandi.com/hdl/zynq/zybo-ov7670-to-vga.html or http://www.instructables.com/id/Connect-Camera-to-Zybo-Board/ for example

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tarinip
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Hello @florentw

 

I have gone through http://www.instructables.com/id/Connect-Camera-to-Zybo-Board

the codes in this are almost same to that of hamesters.I tried with that also but still its showing the same error

 

Thank you

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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

Did you add the block memory generator IP? Do you see it in the sources? Is it the correct name?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tarinip
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Registered: ‎02-02-2017

Hello@florent,

I tried to solve that problem . But  i m getting another problem while implementing  .Could you please go through it

error2.png
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florentw
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Registered: ‎11-09-2015

Hi @tarinip,

 

Your screenshot contains an older version of the synthesized design. Could you reload it?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tarinip
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Registered: ‎02-02-2017

Hello @florentw

 

Here is reloaded design and error in implementation

 

 

Errors in synthd des.png
error in synthd design.png
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