cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
1,045 Views
Registered: ‎04-01-2016

Inverted clock for SPI

Hi all,

 

I have to implement the sources from an ASIC design in a FPGA for rapid prototyping. My ASIC colleagues use for an SPI implementation sck and sck_n. The inverted clock is just used for a few registers. The design is syntactically correct and I can see the RTL after the elaboration phase:

 

 

SPI_SCK_1.png

 

One requirement is not to change the ASIC VHDL sources of course. The spi_sck is a clock capable pin. So my question is, if it is valid to to the following thing:

 

sck_n <= not sck;

-- design instantation

spi_core_inst : entity work.spi_core
port map (
    sck <= sck;
    sck_n <= sck_n
    ...
);

I think this should be valid, because every slice can invert the clock, so is this done by the synthesis tool automatically?

 

SPI_SCK_2.png

 

I run synthesis and implementation and post here a screenshot from implementation view:

 

SPI_SCK_3.png

 

So I think this is exactly what I expected. Nonetheless I would like to know if this is a flow Xilinx recommends. As already told I cannot modify the VHDL files from the ASIC designers because we want to prototype exactly that sources in the FPGA. So the output really looks good (IS_C_INVERTED) and I would like to proceed with this workflow.

 

Kind regards

Sebastian

0 Kudos
1 Reply
Highlighted
Moderator
Moderator
941 Views
Registered: ‎01-16-2013

Re: Inverted clock for SPI

@sebastian_z,

 

Yes, this looks correct. Try running post synthesis functional simulation and see the functionality. 

IS_C_INVERTED specifies the polarity on clock pin.

 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos