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Explorer
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Registered: ‎09-14-2018

KCU105 IPI Design Write Bitstream ERROR IO constraints

I tried to recompile (in Vivado 2018.3) and generate bit file from the KCU105 IP Integrator example design (rdf0313-kcu105-ipi-c-2017-3.zip ), but bitstream generator failed due to the IO constraints issues:

 [DRC NSTD-1]Unspecified I/O Standard: …

[DRC UCIO-1]Unconstrained Logical Port: 23 out of 402 logical ports have no user assigned specific location constraint (LOC)…

I have attached the Vivado messages and the system.xdc file.

How the original image was generated? It appears there is a number of upper/low case mismatches in the constraint file.

Thank you.

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6 Replies
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Registered: ‎01-22-2015

Re: KCU105 IPI Design Write Bitstream ERROR IO constraints

@arotenst 

To keep us on our toes:

VHDL (and some other HDL) is case insensitive when it comes to signal names and port names.

However, Tcl/XDC is case sensitive

So, the case of signal/port names used in both HDL and in constraints (Tcl/XDC) must match.

Case mismatch appears to be the reason for the ERRORS you are getting.

Mark

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Explorer
Explorer
471 Views
Registered: ‎09-14-2018

Re: KCU105 IPI Design Write Bitstream ERROR IO constraints

Hello Mark,

I understand this. This project is the example (or reference) design for the evaluation board with the provided FPGA images. How were they generated if the constraint files are bad? 

How can I get the corrected package?

Thank you.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: KCU105 IPI Design Write Bitstream ERROR IO constraints

Hi @arotenst ,

Please check this AR# for details on this error:

https://www.xilinx.com/support/answers/56354.html

Thanks,

Raj

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Registered: ‎09-14-2018

Re: KCU105 IPI Design Write Bitstream ERROR IO constraints

My original question was why the constraint file of the reference design does not match the design, and if it would possible to get the right file.

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Re: KCU105 IPI Design Write Bitstream ERROR IO constraints

Hi @arotenst ,

I just checked that in the original design (which is provided for Vivado 2017.3) pins vid_io_out_field, vid_io_out_hblank, vid_io_out_vblank, qspi1_sck_io are commented in system_wrapper.v and for other pins, case matches with what we see in system.xdc (this mismatch in 2018.3 is the reason for failure as mentioned in markg@prosensing.com 's reply). So may I know how did system_wrapper.v file change while you migrated from 2017.3 to 2018.3 ? Are you facing any issue while using design with 2017.3 ?

Regards,
Ashish
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Explorer
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Registered: ‎09-14-2018

Re: KCU105 IPI Design Write Bitstream ERROR IO constraints

Hi Ashish,

I have exactly the same files system.xdc and system_wrapper.v in Vivado 2018.3.

I never tried 2017.3 as I de-installed it a long time ago. Vivado 2018.3 is my current revision, no change is welcome due to a number of reasons.

Surprisingly, the conversion from 2017.3 to 2018.3 was smooth except the Ethernet IP, which turned out to be sensitive to the license.

Thank you.

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