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cbemlahe
Explorer
Explorer
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Registered: ‎09-18-2007

MIG User Clocks CLOCK_ROUTE Constraint

I am using the MIG DDR3 1.4 IP core. The DDR3 all works fine on the bench.

In order to reduce/simplify my clock domains, I'm using 100 MHz from the MIG and a secondary 300 MHz output from the MIG for my NAND controller.

My design consistently meets timing but I'm having some issues with NAND memory that is using these two clocks. Is there a way to use the CLOCK_ROUTE constraint on the MIG's user clocks please?

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syedz
Moderator
Moderator
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Registered: ‎01-16-2013

@cbemlahe 

 

Do you mean CLOCK_ROOT or CLOCK_DEDICATED_ROUTE constraints? I don't think any CLOCK_ROUTE property exists. You should find the details of all properties in UG912:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug912-vivado-properties.pdf 

 

Also refer to Ultrafast design methodology user guide: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug949-vivado-design-methodology.pdf 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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