I'm designing a complex system in Spartan7 with Verilog, in which all blocks are present except one after running implementation. I've also isolated the block in a new design, but it is also missed. Simulation runs correctly. Any idea?
Thank for your help.
Top module:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02.10.2019 17:47:42
// Design Name:
// Module Name: kkLina
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module kkLina(
input dIn,
input Clk,
input Enab,
output Out
);
Receptor rxItem(.DataIn(dIn), .ClkModem(Clk), .Enable(Enab), .Valid(Out));
endmodule
Receptor module:
`timescale 1us / 100ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01.10.2019 11:48:52
// Design Name:
// Module Name: Receptor
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Receptor(
input DataIn,
input ClkModem,
input Enable,
output reg Valid
);
parameter eIni = 'b00, eEnabled = 'b01, eFinal = 'b10;
reg [1:0] estado;
reg [`NumBitsPattern - 1:0] valor;
// initial
// Valid = 0;
always @(posedge Enable or negedge ClkModem or posedge ClkModem) begin
if ((Enable == 0) && (ClkModem == 1)) begin
Valid <= 0;
estado <= eIni;
valor <= 'b000000;
end // if ((Enable == 0) && (ClkModem == 1)) begin
else begin
case (estado)
eIni: begin
if ((Enable == 1) && (ClkModem == 1))
estado <= eEnabled;
end // eIni: begin
eEnabled: begin
if ((Enable == 1) && (ClkModem == 0)) begin
valor = {valor, DataIn};
if (valor == `Pattern) begin
estado <= eFinal;
Valid <= 1;
end // if (valor == 'b10001) begin
end // if ((Enable == 1) && (ClkModem == 0)) begin
end // eEnabled: begin
eFinal: ;
default: begin
Valid <= 0;
estado <= eFinal;
end // default: begin
endcase // case (estado)
end // else begin
end // always @(posedge Enable or negedge ClkModem or posedge ClkModem) begin
endmodule // module Receptor();
module Receptor_testbench();
reg dIn;
reg clk;
reg enab;
wire valid;
Receptor testReceptor(.DataIn(dIn), .ClkModem(clk), .Enable(enab), .Valid(valid));
initial begin
clk=0;
enab = 0;
dIn = 0;
end // initial begin
initial begin: clkLoop
forever #5 clk=~clk;
end // initial begin: clkLoop
initial begin
#11 enab = 1;
#15 dIn = 1;
#10 dIn = 0;
#30 dIn = 1;
#10 dIn = 0;
#20 enab = 0;
#100 disable clkLoop;
#1 $finish;
end
endmodule // module Receptor_testbench();
