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chowderii
Contributor
Contributor
334 Views
Registered: ‎01-21-2019

Need help fixing OPT 31-67 ALUT3 Cell is missing a connection on input pin I0

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Hello,

As title suggests, I have this error when I run implementation on my design :

[Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_2_i/toplevel_ssdmobilene_0/U0/iterations_controller/num_slice_to_fill[10]_i_1.

 AR# 72980 suggests to look at the connection schematic to see for a missing connection but it is connected in my case.

chowderii_0-1612962370513.png

 

Thanks!

 

 

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hongh
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Registered: ‎11-04-2010

Please expand hier module "test_slave_lite_0" to see whether there is a primitive as a driver.

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Please expand hier module "test_slave_lite_0" to see whether there is a primitive as a driver.

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syedz
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Registered: ‎01-16-2013

@chowderii  

 

Check this answer record to debug and resolve the error:  https://www.xilinx.com/support/answers/72980.html 

 

--Syed

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chowderii
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Contributor
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Registered: ‎01-21-2019

This is the answer that helped me. I mis-wired one of the registers from the AXI_Lite interface which caused the port to not be connected to anything.

Thank you!

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