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jsy524
Observer
Observer
1,470 Views
Registered: ‎07-15-2018

NgdBuild:604 error

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Hello,

 

I have trouble in translating my project.

I have one schematic file as top module.

Below that, there are 4 v.files (wave1,wave2,wave3,wave4).

When I translate my top module, error appears.

 


ERROR:NgdBuild:604 - logical block 'XLXI_213' with type 'wave3' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   case mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'wave3' is not supported in target
   'xc9500xl'.
ERROR:NgdBuild:604 - logical block 'XLXI_214' with type 'wave2' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   case mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'wave2' is not supported in target
   'xc9500xl'.
ERROR:NgdBuild:604 - logical block 'XLXI_249' with type 'wave4' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   case mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'wave4' is not supported in target
   'xc9500xl'.


 

I searched posts that have same error but couldn't find solution.

Others say that find the edif file and ngc file, and put them in the same path.

However I can't find my edif,ngc file and I don't know how to make them.

Please help me to solve this.

 

Thank you.

 

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1 Solution

Accepted Solutions
syedz
Moderator
Moderator
1,490 Views
Registered: ‎01-16-2013

@jsy524

 

This happens if the Verilog module contains any capital letters. The symbol for the Verilog module is correctly created and added to the schematic file. However, sch2vhdl does not retain capitalization when the intermediate ".vhf" is written out. Therefore, since Verilog is case sensitive, the synthesis tool looks for the module name with all lower case letters. Because the module does not exist with all lower case letters, the synthesis tool creates a black box for the component. NGDBUILD then fails because there is not a netlist to match black box.  

 

There are three ways to work around this problem: 

 

1. Rename the Verilog module to use all lowercase letters. Re-synthesize, and the module should be picked up correctly. 

2. Change the 'Generated Simulation Language' to Verilog. Sch2verilog will be run instead of sch2vhdl, and the module case will be correctly maintained. 

3. Edit the intermediate "<schematic_name>.vhf" file and change the module declaration to the proper case. Note that this is a short-term work-around as the "<schematic_name>.vhf" file will be re-written before synthesis if the schematic file has been touched.

 

--Syed

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6 Replies
syedz
Moderator
Moderator
1,436 Views
Registered: ‎01-16-2013

@jsy524,

 

Did you see any warning message in synthesis? Check on if the block name exactly matches to the one present in top module.

Can you share the complete ISE project?

 

--Syed

 

 

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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jsy524
Observer
Observer
1,431 Views
Registered: ‎07-15-2018

 

I got warning messages but I'm not sure that they are related to this error.

Block name matches well so it would not be a problem.

I submit my project file as zip file.

 

 

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syedz
Moderator
Moderator
1,428 Views
Registered: ‎01-16-2013

@jsy524

 

The file in your previous post has only .xise file with which we cannot reproduce the error. 

From ISE GUI, select Project-->Archive.. This will save your project in .zip file. Please share this tool generated file. 

Capture.JPG

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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jsy524
Observer
Observer
1,426 Views
Registered: ‎07-15-2018

 

Sorry for my mistake.

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syedz
Moderator
Moderator
1,491 Views
Registered: ‎01-16-2013

@jsy524

 

This happens if the Verilog module contains any capital letters. The symbol for the Verilog module is correctly created and added to the schematic file. However, sch2vhdl does not retain capitalization when the intermediate ".vhf" is written out. Therefore, since Verilog is case sensitive, the synthesis tool looks for the module name with all lower case letters. Because the module does not exist with all lower case letters, the synthesis tool creates a black box for the component. NGDBUILD then fails because there is not a netlist to match black box.  

 

There are three ways to work around this problem: 

 

1. Rename the Verilog module to use all lowercase letters. Re-synthesize, and the module should be picked up correctly. 

2. Change the 'Generated Simulation Language' to Verilog. Sch2verilog will be run instead of sch2vhdl, and the module case will be correctly maintained. 

3. Edit the intermediate "<schematic_name>.vhf" file and change the module declaration to the proper case. Note that this is a short-term work-around as the "<schematic_name>.vhf" file will be re-written before synthesis if the schematic file has been touched.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

jsy524
Observer
Observer
1,364 Views
Registered: ‎07-15-2018

 

Thanks for your help:)

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