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Registered: ‎01-15-2019

[Opt 31-67] @ 10G Ethernet PCS/PMA IP @opt_design - P&R problem - how to solve?

Hi All,

I'm receiving the following error while opt_design stage:

[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: i_pcs_pma/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/inst/ten_gig_eth_pcs_pma_0_local_clock_reset_block/sim_speedup_controller_inst/simple_delay_inst_i_1.

It seems that the problem is in the sim_speedup_control input, which I left unconnected in the RTL instance of the ten_gig_eth_pcs_pma_core instance... Should I really connect it? I thought it's just for a simulation only... As for the physical implementation, should I tie it to HIGH constantly?

Thank you!

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Registered: ‎11-04-2010

Re: [Opt 31-67] @ 10G Ethernet PCS/PMA IP @opt_design - P&R problem - how to solve?

Hi, @ldm.eth ,

To workaround the error during opt_design temporarily, you can set the pin I1 of LUT to "1" or "0" before opt_design.

Ex: set_logic_zero [get_pins i_pcs_pma/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/inst/ten_gig_eth_pcs_pma_0_local_clock_reset_block/sim_speedup_controller_inst/simple_delay_inst_i_1/I1]

For how to connect the  sim_speedup_controlof ten_gig_eth_pcs_pma_core instance, you need to consult IP engineer in IP board:

(Community Forums->Forums->Intellectual Property-> Networking and Connectivity)


Don't forget to reply, kudo, and accept as solution.
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