[Opt Design] Memory Core Error after copying project files to another location

[uxxexzer]

I copied a project to a new directory and now I get memory core error: 

c0_ddr4_bg has an invalid IOSTANDARD LVCMOS18 is selected. Valid IOSTANDARD for this port include SSTL12_DCI.

Attached is the image showing the error. 

Any thoughts?

[hongh]

Please confirm your physical constraints XDC including DDR's IO ports' IO standard and package_pin property is also copied properly for the new project.

You can also try to recreate the MIG core after checking the first item. 

[uxxexzer]

Hi @hongh,
Thank you for the quick reply.

XDC file is included in the new project though there is no mention of DDR's IO ports' IO standard in XDC.

The affected ports are ONLY mentioned in the XDC as follows:
set_property PACKAGE_PIN AV23 [get_ports {c0_ddr4_bg[0]}]
set_property PACKAGE_PIN AT27 [get_ports {c0_ddr4_bg[1]}]

How can I regenerate the MIG core?

Thanks in advance.

[hongh]

What's the IOSTANDARD of the reported ports in the new and original project?

get_property IOATANDARD [get_ports {c0_ddr4_bg[0]}]
get_property IOATANDARD [get_ports {c0_ddr4_bg[1]}]

[uxxexzer]

In the original project and taken from Implementation, the tcl command returned SSTL12_DCI.
In the new project and taken from Synthesis, the tcl command returned LVCMOS18. I was not able to complete Implementation in the new project due to the opt_design error.

[hongh]

In the original project, export the XDC with "write_xdc XX.xdc"  and check where the IOATANDARD SSTL12_DCI constraints are involved.

You can try to add the below constraints in your new project's XDC:

set_property IOATANDARD SSTL12_DCI [get_ports {c0_ddr4_bg[0]}]
set_property IOATANDARD SSTL12_DCI [get_ports {c0_ddr4_bg[1]}]

[uxxexzer]

Yes, they are constrained in a pcie_xdma_ddr4_0_0.xdc which is part of the IP sources:
set_property IOSTANDARD SSTL12_DCI [get_ports {c0_ddr4_bg[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {c0_ddr4_bg[1]}]

This XDC file is also present in the new project but the constraints above are not present. 

This is the XDC file is both in the old and new projects:
new_project.srcs/sources_1/bd/pcie_xdma/ip/pcie_xdma_ddr4_0_0/par/pcie_xdma_ddr4_0_0.xdc
old_project.srcs/sources_1/bd/pcie_xdma/ip/pcie_xdma_ddr4_0_0/par/pcie_xdma_ddr4_0_0.xdc

Why was it not reflected in the new project?
Is it better to regenerate the MIG core? How?

I would like to understand this first before manually adding the constraints in the new project as the pcie_xdma_ddr4_0_0.xdc has 349 lines.
Thank you.

[hongh · Accepted solution]

You can try to reset and generate the output for the bd design first.

[uxxexzer]

After resetting, should I generate the output products or can I proceed to Synthesis directly?

If generating output products, what options should I select?

[hongh]

Any of the options can be selected.

Global: The bd design will be synthesized with the whole design.

Out of context per IP: Synthesize every IP independently in BD 

Out of context per Block design: Synthesize the whole BD design directly.

[uxxexzer]

Hi @hongh,

After resetting output products, I proceeded with Synthesis directly.
After synthesis has completed, I executed
- get_property IOSTANDARD [get_ports {c0_ddr4_bg[0]}]
- get_property IOSTANDARD [get_ports {c0_ddr4_bg[1]}]
and yielded SSTL12_DCI, which what we expected.

Then, I proceeded with Implementation and Generate Bitstream and completed both of these steps successfully.

I will read up on the different options for Generating Output Products for reference in the future.

Thank you very much for your time and effort for answering my queries.
That's all for now.