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Observer
Observer
12,408 Views
Registered: ‎10-08-2009

PCIE Core Constrait Problems

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I'm using a Virtex7 FPGA 458T when I genereate the PCIE GEN 2 8 lane core in Vivado i automatically has an .xdc file that places my transceivers in a location I don't want them to be. I want them on

 

MGT_117 and MGT116

 

but it is placing it in

 

MGT117 and MGT118

 

I place a LOC constraint in my xdc file but it gets an error:

 

 

[Vivado 12-2285] Cannot set LOC property of instance '....gtx_channel.gtxe2_channel_i', Instance ...i/gtx_channel.gtxe2_channel_i can not be placed in GTXE2_CHANNEL of site GTXE2_CHANNEL_X1Y19 because the bel is occupied by .gtxe2_channel_i. This could be caused by bel constraint conflict ["_pci_nn_485t_vivado.xdc":100]

 

 

 

The PCIE wizards should allow you to select MGTs but it doesn't. How do I tell vivado to ignore the .xci genereated and use the xdc file on my toplevel instead?

 

Without having to remove the .xci file and adding all source by hand.

 

 

 

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Voyager
Voyager
24,361 Views
Registered: ‎01-28-2008

You can disable the .xdc inside the IP and copy/modify it and add it to the project. You may need to add a SCOPED_TO_REF/CELLS to the xdc or modify the hierarchical paths to match your design's.

https://tuxengineering.com

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Voyager
Voyager
24,362 Views
Registered: ‎01-28-2008

You can disable the .xdc inside the IP and copy/modify it and add it to the project. You may need to add a SCOPED_TO_REF/CELLS to the xdc or modify the hierarchical paths to match your design's.

https://tuxengineering.com

View solution in original post

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