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WH1
Visitor
Visitor
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Registered: ‎08-13-2020

Place 30-120: Sub-optimal placement for a BUFG-BUFG cascade pair

Hello all,

 

I am working on a project for a board with a Xilinx Zynq 7010 SoC. 

I went to generate the bitstream of my project and came accross the following error: 

 

[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets system_i/PS7/processing_system7_0/inst/FCLK_CLK0] >

system_i/PS7/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y12
system_i/Counting/bram_switch_1/inst/BUFGMUX_inst (BUFGCTRL.I1) is provisionally placed by clockplacer on BUFGCTRL_X0Y15
system_i/Counting/bram_switch_0/inst/BUFGMUX_inst (BUFGCTRL.I1) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_cascaded_bufg
Status: PASS
Rule Description: Cascaded bufg (bufg->bufg) must be adjacent and cyclic
system_i/DataAcquisition/axis_red_pitaya_adc_0/inst/adc_clk_inst (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
system_i/Counting/bram_switch_1/inst/BUFGMUX_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y15
system_i/Counting/bram_switch_0/inst/BUFGMUX_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

Clock Rule: rule_gclkio_bufg
Status: PASS
Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip
as the BUFG
system_i/DataAcquisition/axis_red_pitaya_adc_0/inst/adc_clk_inst0 (IBUFDS.O) is locked to IOB_X0Y26
system_i/DataAcquisition/axis_red_pitaya_adc_0/inst/adc_clk_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

Clock Rule: rule_ps7_bufg
Status: PASS
Rule Description: A PS7 driving a BUFG must be placed on the same half side (top/bottom) of the device
system_i/PS7/processing_system7_0/inst/PS7_i (PS7.FCLKCLK[0]) is locked to PS7_X0Y0
and system_i/PS7/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y12

 

From what I've read in other issues on this forum + xilinx documentation this has to do with the placement rules for the BUFGs. I tried following the forum post from a4speaker in 2014 about the same topic, but noticed they had different Clock Rules in their error message. I am unsure how to proceed, any help resolving this would be greatly appreciated. I am a beginner with this aspect of Vivado so any and all help is appreciated. 

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8 Replies
hongh
Moderator
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625 Views
Registered: ‎11-04-2010

Please refer to AR-54962

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chinmays
Xilinx Employee
Xilinx Employee
611 Views
Registered: ‎06-27-2018

Hi @WH1,

In 7 series, if there are cascaded BUFGs then they should be placed on adjacent BUFG sites, within the group of 16 in either upper or lower half. Please have a look at UG472-cascading BUFGs and AR#54962.

~Chinmay

WH1
Visitor
Visitor
552 Views
Registered: ‎08-13-2020

I see, thank you both for your responses.  I'm not sure how many cascaded BUFGs (or BUFGs for that matter) my design has, nor how to locate them. I have some idea on how to solve this based on the forum post linked below but am overall unsure, and hesitant to poke around in the synthesized design. 


From what I read in the following forum thread https://forums.xilinx.com/t5/Implementation/Sub-optimal-placement-for-a-BUFG-BUFG-cascade-pair-gt-how-to/td-p/725993 this problem can be rectified by manually moving the cascaded BUFGs so that they are in the same half in the GUI or using the "Loc" command. However I am unsure of my clock structure (on the level shown in the linked forum post), as well as if the same fix would solve my issue. Any help is appreciated

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chinmays
Xilinx Employee
Xilinx Employee
509 Views
Registered: ‎06-27-2018

Hi @WH1,

If you are worried about ruining your synthesized design, the best way is to experiment on a post-opt DCP instead of the project. To create post-opt DCP, open synthesized design and run "opt_design" (without quotes) from tcl console. Once it completes, run "write_checkpoint ./post_opt.dcp". This will generate the dcp in your cwd. Close the project and open the post_opt.dcp in Vivado. Now you can apply the suggestions on the DCP.

About locating the Problematic BUFG placements, its all given in the error message. After you open post-opt dcp in Vivado, run "place_ports" from tcl console, this will place the BUFGs provisionally on the device. You can run show_objects command to show a particular BUFG/cell on the device, 

ex: show_objects [get_cells system_i/PS7/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG]

~Chinmay 

 

WH1
Visitor
Visitor
493 Views
Registered: ‎08-13-2020

Thank you for that suggestion about the checkpoint, that helps a lot. Just to confirm I understand your statements, are you saying that using the tcl command "place_ports" should solve the problem without manual placement of the BUFGs? If not and I need to place them manually, I have an idea of how to do that based on the issue I previously linked.

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syedz
Moderator
Moderator
475 Views
Registered: ‎01-16-2013

@WH1 

 

place_ports will not solve the problem. It can be used to debug the clock placer error. Check this AR: https://www.xilinx.com/support/answers/67203.html 

 

--Syed

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WH1
Visitor
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443 Views
Registered: ‎08-13-2020

 Hello,
Thank you for that link, upon following the instructions there I gained more insight into the error and clock utilization in general.

I have what I believe to be my final question on this issue: how do I know where to place the cascaded BUFGs mentioned in the error message such that they're adjacent and the remainder of the design is not disturbed? From what I understand from https://forums.xilinx.com/t5/Implementation/Sub-optimal-placement-for-a-BUFG-BUFG-cascade-pair-gt-how-to/td-p/725993, this placement can be anywhere as long as the BUFGs are adjacent. How do you know this?

I've also attached two files: the output of the "report_clock_utilization -write_xdc switch" command in the tcl command line, and the switch file itself. I was having trouble attaching the switch.xdc file with the .xdc file type, so I just saved its contents into a text file of the same name. I believe I understand the problem and how to fix it now- if I'm correct, I need to move the problematic BUFGs to adjacent locations, which can be done using either the "Loc" command or the GUI (use of the GUI described in forum post https://forums.xilinx.com/t5/Implementation/Sub-optimal-placement-for-a-BUFG-BUFG-cascade-pair-gt-how-to/td-p/725993). If my understanding is correct, I can open the synthesized design (before opt_design and place_ports has been run), and run "LOC BUFGCTRL_XxYy ..." in the tcl command line to place the bram_switch_0 BUFG near the other two BUFGs mentioned in the error message. Thank you for your help.

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WH1
Visitor
Visitor
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Registered: ‎08-13-2020

Hello @syedz@chinmays, and @hongh,

I've played around with manually setting the location of the BUFGs listed in the error message (using the tcl command line), and the design has continued to fail the implementation step. I've tried manually placing them in spots that have allowed for the implementation to complete in similar designs, but the implementation has yet to be successful. Now that I'm confident in my ability to manually place the BUFGs and save the changes to the cfg file, my main question is: where should I place the BUFGs to avoid the error, and how do you know those locations will resolve the issue. 

Thank you for your time.

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