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Registered: ‎11-20-2017

Place design issue. ERROR: [DRC REQP-127]

When I tried to implement my design using TCL scripts the following error occurred.

 

Place design issue.

ERROR: [DRC REQP-127] obuf_loaded: OBUF pulpino_wrap_i/gpio_out_OBUF[16]_inst pin O drives one or more invalid loads. The loads are: ps7_wrapper_i/ps7_i/axi_gpio_emu/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to

 

I am new to using vivado tool chain and would be glad if some one could help. This error occurred on Vivado 2017.3 .:)

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Registered: ‎11-09-2015

Re: Place design issue. ERROR: [DRC REQP-127]

Hi @rangana_desilva,

 

Open the synthesized design and try to find fo this net. It might help you to understand what is wrong.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-20-2017

Re: Place design issue. ERROR: [DRC REQP-127]

Hi,

 

I opened the synthesis design and opened the DRC report and find out these error messages. What is meant by pin 0 having one or more invalid loads and is there a fix for that using TCL script files?

I attached the drc report screenshot! :)

 

Thank you,

rangana

Screenshot from 2017-11-21 11-22-46.png
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Registered: ‎11-09-2015

Re: Place design issue. ERROR: [DRC REQP-127]

Hi @rangana_desilva,

 

This does not give more detail. Open the synthesized design and looked for the mentioned net in the schematic view (try to find in in the netlist and use F4 to show it on the schematic view)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-20-2017

Re: Place design issue. ERROR: [DRC REQP-127]

Hi,

This is the schematic. The error says

"REQP #1 Error OBUF pulpino_wrap_i/gpio_out_OBUF[16]_inst pin O drives one or more invalid loads.The loads are:ps7_wrapper_i/ps7_i/axi_gpio_emu/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to  "

 

 

 

Screenshot from 2017-11-21 12-35-12.png
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Registered: ‎11-09-2015

Re: Place design issue. ERROR: [DRC REQP-127]

Hi @rangana_desilva,

 

So on the schematic we can see the issue: an OBUF should not drive a FDRE. You need to modify your design to avoid it (the outbuf should be connected only to a pin of the FPGA)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-20-2017

Re: Place design issue. ERROR: [DRC REQP-127]

Hi,

Thank you for the reply and I have few questions.

How  do I modify the design, which files and the procedure I should follow.

 

Thank you,

Rangana.

 

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Registered: ‎11-09-2015

Re: Place design issue. ERROR: [DRC REQP-127]

Hi @rangana_desilva,

 

I don't know your design but you might need to change a file called pulpino_wrap


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-20-2017

Re: Place design issue. ERROR: [DRC REQP-127]

hi,

 

I am trying to run a vivado project implemented on vivado 2015.1 in vivado 2017.3. Are there any specific changes to make to the script files to get it run on newer version of vivado. 

 

Thank you,

Rangana.

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Registered: ‎11-09-2015

Re: Place design issue. ERROR: [DRC REQP-127]

Hi @rangana_desilva,

 

It depends on your script file. But in most cases, the answer is yes


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-20-2017

Re: Place design issue. ERROR: [DRC REQP-127]

What kind of changes occur in script files. Is it that the previous script commands are no longer valid in the new vivado versions. Where can I find all the changes and modifications done to script commands from 2015.1 to 2017.3 vivado version. 

 

I did few changes, 

in ps7_bd.tcl

 

1.set scripts_vivado_version 2017.3 from set scripts_vivado_version 2015.1

 

in run.tcl

1. #synth check point mode none
set_property synth_checkpoint_mode None [get_files ./pulpemu.srcs/sources_1/bd/ps7/ps7.bd] 

 

no changes made on impl.tcl

 

With doing these changes I was able to complete the synthesize stage but implementation failed with place design error as mentioned above in this thread. You said modify the OBUF connection , but I don't know how it should be done using this tcl scripts. Hope you can help me out with this. :) (And let me know if there are any depreciated script commands as this was written using vivado 2015.1 and now been run on 2017.3)

 

I've attached all three tcl files. Hope it helps to identify the locations i have to change. 

 

 

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Registered: ‎11-09-2015

Re: Place design issue. ERROR: [DRC REQP-127]

HI @rangana_desilva,

 

What kind of changes occur in script files. Is it that the previous script commands are no longer valid in the new vivado versions. Where can I find all the changes and modifications done to script commands from 2015.1 to 2017.3 vivado version. 

> This is not really documented. You need to look individually to the command which are different.

 

With doing these changes I was able to complete the synthesize stage but implementation failed with place design error as mentioned above in this thread. You said modify the OBUF connection , but I don't know how it should be done using this tcl scripts. Hope you can help me out with this. :) (And let me know if there are any depreciated script commands as this was written using vivado 2015.1 and now been run on 2017.3)

> You only have scripts? No HDL files?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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