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Visitor mfj_silicom
Visitor
197 Views
Registered: ‎05-11-2018

Possible bug in Vivado 2019.1 with directive NoBramPowerOpt

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I have a design targeted for the Artix-7 FPGA. I'm using Vivado 2018.3 and everything works as expected.

But when I upgrade to Vivado 2019.1, the design fails. In the schematic view I notice that a ROM is missing some data pins that should be there.

There are no changes to the design, the only change is using Vivado 2019.1 instead of 2018.3.

After some more debugging I find out that in the failing design I use the command "opt_design -directive NoBramPowerOpt". If I remove the directive (but keep the opt_design) then the design works find in both 2018.3 and 2019.1.

So it looks like *disabling* BRAM power optimizations is causing problems in the latest versions of Vivado.

Is this a known bug? The obvious workaround is to leave BRAM power optimizations enabled.

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Xilinx Employee
Xilinx Employee
121 Views
Registered: ‎05-22-2018

Re: Possible bug in Vivado 2019.1 with directive NoBramPowerOpt

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Hi @mfj_silicom ,

Please close the thread by marking as accepted solution if no further conerns are there.

Thanks,

Raj

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Visitor mfj_silicom
Visitor
179 Views
Registered: ‎05-11-2018

Re: Possible bug in Vivado 2019.1 with directive NoBramPowerOpt

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Please ignore this topic. I made a mistake when looking at the schematic.

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Xilinx Employee
Xilinx Employee
122 Views
Registered: ‎05-22-2018

Re: Possible bug in Vivado 2019.1 with directive NoBramPowerOpt

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Hi @mfj_silicom ,

Please close the thread by marking as accepted solution if no further conerns are there.

Thanks,

Raj

View solution in original post

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