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Observer mahkoe
Observer
299 Views
Registered: ‎02-08-2019

Prevent merging output register with BRAM

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I have a Verilog module that looks like this:

//Quick module which Vivado should synthesize as a BRAM
//See the Xilinx Synthesis Technology report for details
module dp_bram # (
    parameter ADDR_WIDTH = 10,
    parameter PORT_WIDTH = 32
) (
    input wire clk,
    
    input wire en,                           //@0
    
    input wire [ADDR_WIDTH-1:0] addra,  //@0
    input wire [ADDR_WIDTH-1:0] addrb,  //@0

    input wire [PORT_WIDTH-1:0] dia,    //@0
    input wire [PORT_WIDTH-1:0] dib,    //@0
    input wire wr_en,                   //@0
    
    output reg [PORT_WIDTH-1:0] doa,    //@1
    output reg [PORT_WIDTH-1:0] dob     //@1
);
    reg [PORT_WIDTH-1:0] data [0:2**ADDR_WIDTH-1];

    always @(posedge clk) begin
        if (en) begin
            if (wr_en == 1'b1) begin
                data[addra] <= dia;
            end
            doa <= data[addra]; //Read-first mode
        end
    end

    always @(posedge clk) begin
        if (en) begin
            if (wr_en == 1'b1) begin
                data[addrb] <= dib;
            end
            dob <= data[addrb]; //Read-first mode
        end
    end
endmodule

Elsewhere in my design, I connect the output of this BRAM directly to a register, in order to ease timing. 

Somewhere along the way, Vivado merged this output register into the BRAM itself, which is not necessarily a problem. However, the logic which drives the reset line of the output register is failing timing, since it has to be routed all the way over to the BRAM.

Is there some way to disable this merging of the output register, or is there some other solution which would be better?

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Xilinx Employee
Xilinx Employee
204 Views
Registered: ‎05-08-2012

Re: Prevent merging output register with BRAM

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Hi @mahkoe 

A DONT_TOUCH constraint will prevent optimization on a logic cell. This would be a good way to avoid the change if set on the BRAM or driven FF.

set_property DONT_TOUCH TRUE [get_cells <name_of_instance>]

 

---------------------------------------------------------------------------------------------
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Teacher drjohnsmith
Teacher
294 Views
Registered: ‎07-09-2009

Re: Prevent merging output register with BRAM

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The best option would be to get rid of the reset ,
why do you need a reset is always a good question to ask, as often they are only adding code, slowing the design and not giving one anything,

https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Xilinx Employee
Xilinx Employee
205 Views
Registered: ‎05-08-2012

Re: Prevent merging output register with BRAM

Jump to solution

Hi @mahkoe 

A DONT_TOUCH constraint will prevent optimization on a logic cell. This would be a good way to avoid the change if set on the BRAM or driven FF.

set_property DONT_TOUCH TRUE [get_cells <name_of_instance>]

 

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

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Teacher drjohnsmith
Teacher
174 Views
Registered: ‎07-09-2009

Re: Prevent merging output register with BRAM

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As @marcb says , using the constraint file as you show is great for some things,

but for a module, where its a design need, such as this, I'd put the constraint in the RTL code. That way if the code is re used, the need for separate registers is not lost,

EDIT:  shows the dont_touch constraint int he source code

https://www.xilinx.com/support/answers/54699.html

 

BTW: in the app note, project_1 is empty, look in project_2,

   I Know this a Verilog question, but note there is no VHDL example, in the project of the app note 

        shame on Xilinx 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>