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Adventurer
Adventurer
201 Views
Registered: ‎11-18-2017

Problem in implementation stage: using clock source as an input signal.

 

Hello.

I'm using KCU116 evaluation board ( kintex ultrascale+ FPGA equipped) and Vivado 2018.2.

 

I want to use a external clock source as a input signal to the FPGA.

And with this clock signal, I'm trying to synthesize stable clocks with different frequencies and use them as a data signal or a combinational logic input signal (not as a clock).

In the KCU116 evaluation board, there is a EMCCLK which is running at 90 Mhz (reference : KCU116 Evaluation Board User Guide - UG1239(v1.2) - 30p).

So I used this clk as the signal input source.

 

Below figures are my design and schematic of the input section (the upper MMCM has 'Safe Clock Startup' feature).

ti1_3.JPG

fig1. design

 

t1_1.JPGfig2. schematic

 

However, in the implementation stage, below error ([Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM) occurs (there was no problem in the synthesize stage).

ti1_2.JPG

fig3. error

 

As suggested in the message, I added an BUFG between input port and MMCM, and below figures are my modified design and schematic of the input section (the upper MMCM has 'Safe Clock Startup' feature).

ti2_3.JPG

fig4. design

t2_1.JPG

fig5. schematic

 

However, in the implementation stage, below error ([Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFg pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUNTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged.) occurs (there was no problem in the synthesize stage).

ti2_2.JPG

fig6. error

 

I added the below XDC code as suggested in the message.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets signal_i_IBUF_inst/O]

 

Finally, there was no error.

 

My question is what is the reason why I have to do such procedures (adding BUFG and the XDC code) to use external clock as a input signal

and what is the meaning of 'CLOCK_DEDICATED_ROUTE FALSE'?

 

Thank you very much.

 

6 Replies
Scholar dpaul24
Scholar
183 Views
Registered: ‎08-07-2014

Re: Problem in implementation stage: using clock source as an input signal.

@kimjaewon,

The first error is because you are not bringing in to the FPGA fabric, the clock signals via clock capable pins. This is a recommended design practice. In your case the position of the pin and the MMCM are in different regions, so a BUFG should be manually inserted to route the clock to the MMCM. That is what you have done.

If you would have used a clock capable pin, then a BUFG would not be needed. The MMCM and clock capable pins in FPGAs exist in their vicinity so that routing delay and BUFG delay is reduced (you have minimum clock delays).

Please go through the explanations of these ARs:

https://www.xilinx.com/support/answers/64452.html

https://www.xilinx.com/support/answers/66659.html

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All PMs will be ignored
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Highlighted
154 Views
Registered: ‎01-22-2015

Re: Problem in implementation stage: using clock source as an input signal.

@kimjaewon 

First, thanks for the effort you put into your questions – which are an example for us all to follow.

As @dpaul24 says, the warnings you received often indicate that a clock is being brought into the FPGA on a pin that is not a global clock (GC) pin.  As a result, the dedicated routing path from the GC-pin to the MMCM cannot be used.  When these dedicated routing paths cannot be used then clock quality is degraded.

In your case, I also suspect that EMCCLK is coming into an HD-bank of your UltraScale FPGA.  As explained on page 10 of UG572(v1.8), UltraScale HD banks do not have an MMCM.  Thus, a BUFGCE is needed to route a clock from a pin in a HD-bank to an MMCM in another bank.    

Can you confirm that EMCCLK is entering the FPGA on an HD-bank pin?

Mark

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Xilinx Employee
Xilinx Employee
146 Views
Registered: ‎05-22-2018

Re: Problem in implementation stage: using clock source as an input signal.

Hi @kimjaewon ,

Generally it is not recommended to set clock_dedicated_route false.

Please check page no.104 for brief explanation:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug949-vivado-design-methodology.pdf

Thanks,

Raj

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111 Views
Registered: ‎01-22-2015

Re: Problem in implementation stage: using clock source as an input signal.

@kimjaewon 

On the KCU116 board, the User Guide (UG1239) shows that the FPGA is a XCKU5P-2FFVB676E and that a clock source called EMCCLK is routed to pin-N21.  The package file for XCKU5P-2FFVB676E shows that pin-N21 is in HP-bank #65 and has designation, IO_L24P_T3U_N10_EMCCLK_65.  Table 1-5 in UG575(v1.12) helps us interpret the designation for pin-N21 as follows:

  • IO = user I/O pin
  • L24P = P(positive) side of differential pair, L24
  • T3U =  upper nibble of byte-group 3
  • N10 = total of 10 I/O in this byte group
  • EMCCLK = external clock that could be used for FPGA configuration instead on internal CCLK
  • 65 = bank number

The designation for pin-N21 does NOT have the GC or HDGC designator.  So, pin-N21 is NOT a global-clock pin.  Thus, everything you have done was necessary to route the clock from pin-N21 to an MMCM.

CLOCK_DEDICATED_ROUTE property:
Pins with the global-clock (GC) designation have dedicated routing paths between the pin and a nearby MMCM.  When these dedicated routing paths are used, the MMCM can compensate for delay variations in the path as described on page 56 of UG572(v1.8).  However, when a clock is brought into the FPGA via a pin that is not a GC-pin, then routing of the clock to an MMCM must be done in-part through the FPGA fabric (and we must use CLOCK_DEDICATED_ROUTE=FALSE).  The MMCM is unable to compensate for delay variations in clock routing paths through the FPGA fabric.  The dedicated routing paths and delay compensation for clocks are important only for some applications as described on page 166 of UG912(v2019.1), “…fabric routing may be fine if the clock is only used internally, but the clock will not be usable for any reasonable speed I/O interface.”

MY RECOMMENDATION:
The EMCCLK designator on pin-N21 indicates that the user can send a clock to this pin that could be used instead of the FPGA’s internal CCLK for FPGA configuration (see page-40 of UG570(v1.9.1) for details).   For this reason and because pin-N21 is not a GC-pin, you should (instead of EMCCLK) use one of the other clock sources available on the KCU116 board.  That is, refer to Table 3-6 in UG1239 for other available clock sources and select one that is routed to a GC-pin on the FPGA (eg. SYSCLK_300 or USER_SMA_CLOCK).  However, if you can't follow this recommendation that tell us more about how you are planning to use EMCCLK and we can help you decide whether it is suitable.

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102 Views
Registered: ‎06-21-2017

Re: Problem in implementation stage: using clock source as an input signal.

If you want to use the 10MHz signals from the MMCM as logic signals and not clocks, why not treat the 90 MHz signal as a signal and not a clock?  Synchronize it to the 400MHz clock, then use a counter running on the 400MHz clock to divide it to produce the 10MHz signals.  The Implementation and timing analyser tools will be a lot happier with this.

18 Views
Registered: ‎01-22-2015

Re: Problem in implementation stage: using clock source as an input signal.

@kimjaewon 

    I'm trying to synthesize stable clocks with different frequencies and use them as a data signal or a combinational logic input signal (not as a clock).

If you plan to use the “stable clocks” only as signals, then you can follow the advice of @bruce_karaffa  – and (as Bruce says) keep the tools happier by avoiding the CLOCK_DEDICATED_ROUTE problems.

However, you can simplify things even further by not using FPGA_EMCCLK.  Instead, you can generate the clock-like signals directly from the 400MHz output of the MMCM that you are calling clk_gen.  This type of clock-like signal is called a toggle.  In the following thread, you will find VHDL code examples that generate and use the toggle – as well as a discussion of toggle benefits.

https://forums.xilinx.com/t5/Timing-Analysis/Reducing-long-net-delay-routing/m-p/905620#M15370

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