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Observer rloader
Observer
4,993 Views
Registered: ‎01-22-2011

Problem porting RLOC constraints to Vivado from ISE.

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Hi, I'm having problems getting RLOC constraints to do in Vivado (2013.2) what I had working in ISE (13.4).

 

The thing that I cannot get working in Vivado is creating a single RPM that spans multiple source VHDL modules. I always end up with multiple separate RPMs.

 

Any suggestions/help appreciated!

 

My top-level VHDL module has an RLOC (& RLOC_ORIGIN) constraint on a top-level register, and a RLOC on a sub-module instantiation. The sub-module then has RLOCs on more registers, so the constraints look like:

 

Top-level:

 

attribute rloc of D0 : signal is "X-1Y2 X-1Y2 ...."; -- 32 bits wide in the real code.

attribute rloc of p : label is "X0Y0";

 

and then in the module defining p:

 

attribute rloc of ldA, ldB, ldC, ldD : signal is "X0Y0";

 

In XST, this nicely gets the D0 and ldA placed close to each other, in the relative postions I excpect (D0 slice left 1 up 2 from ldA).

 

But in Vivado, it seems I get two RPMs, one for the top-level registers and one for the sub-module registers, and their relative placement is not what I expected (

 

Adding U_SET constraints to everything does not help. I still get two RPMs, both with the same name (see attached screen shot). I expected the U_SET constraint to force the merging of the two RPMs, even if for some reason Vivado won't do it automatically.

 

Checking the RLOC constraints in the vivado GUI, I can see them on the correct registers. So it definitely appears that the point I am going wrong is the grouping of components into the RPM.

 

In Vivado synthesis I have "-flatten_hierarchy" set to "REBUILT". The design gets no errors or critical warnings, and no wanings mentioning placement or the RLOC constraints. The target device is artix xc7a200ftbg676-2.

 

Cheers,

Ralph.

 

PS. I'm sure someone will ask whether I still need the RLOCs with Vivado - the answer is yes, Vivado does a fantastically better job of placement than ISE, but this design still needs some hand placement.

u_set_rpms.png
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Xilinx Employee
Xilinx Employee
7,904 Views
Registered: ‎07-01-2008

Re: Problem porting RLOC constraints to Vivado from ISE.

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There are some known problems with how Vivado accumulates RLOCs from multiple hierarchy levels with CRs scheduled to be fixed in future releases. For now I suggest that you just apply RLOCs to the instance directly along with the U_SET value to define the set membership.

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Xilinx Employee
Xilinx Employee
7,905 Views
Registered: ‎07-01-2008

Re: Problem porting RLOC constraints to Vivado from ISE.

Jump to solution

There are some known problems with how Vivado accumulates RLOCs from multiple hierarchy levels with CRs scheduled to be fixed in future releases. For now I suggest that you just apply RLOCs to the instance directly along with the U_SET value to define the set membership.

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