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fkhalili
Adventurer
Adventurer
2,090 Views
Registered: ‎11-06-2017

Problem regarding Vivado 2017.3 bitstream generation

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Hi, 

I have a problem at bitstream generation in Vivado 2017.3.  I am using the same project which has already worked in Vivado 2017.2, In the other words, I am migrating my project from 2017.2 to 2017.3. But in Vivado 2017.3 I have following errors: 

[DRC NSTD-1] Unspecified I/O Standard: 8 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), ... . . . . . ...  

In fact I have defined for all ports their related IO Standards. But I don't know why the vivado shows this error! 

P.S. The platform that I use is " xczu9eg-ffvc900-1-e-es2" 

Thank you 

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1 Solution

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florentw
Moderator
Moderator
3,162 Views
Registered: ‎11-09-2015

Hi @fkhalili,

 

Could you share a log file?

 

The log file should tell you if there are constraints that are not taken in account.

 

What if you open the implemented design an you select the IO planning view? Do you see the IO standard are still Default?

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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fkhalili
Adventurer
Adventurer
2,088 Views
Registered: ‎11-06-2017

Sorry, I forgot to mention that I also updated the version to 2017.3.1 but the problem still exists! 

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thakurr
Moderator
Moderator
2,063 Views
Registered: ‎09-15-2016

Hi @fkhalili

 

Can you share the project to reproduce it at our end? Once we reproduce it we can report it to the factory.

Meanwhile you can work around this following the steps in the AR below:

https://www.xilinx.com/support/answers/56354.html

 

Regards

Rohit

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Regards
Rohit
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fkhalili
Adventurer
Adventurer
2,041 Views
Registered: ‎11-06-2017

Dear @thakurr,

Thanks for your reply. I am so sorry, because of respecting to the regulations of my employer, I cannot share the project! So, I am switching back to 2017.2 . I would also give a feedback about this issue. 

Kinds,
Farnam

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florentw
Moderator
Moderator
3,163 Views
Registered: ‎11-09-2015

Hi @fkhalili,

 

Could you share a log file?

 

The log file should tell you if there are constraints that are not taken in account.

 

What if you open the implemented design an you select the IO planning view? Do you see the IO standard are still Default?

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

fkhalili
Adventurer
Adventurer
1,820 Views
Registered: ‎11-06-2017

Dear @florentw

Sorry for the delayed reply. Due to lack of time to deliver the project I had to switch back to 2016.3 version and unfortunately I have not access to the log files since the project using in 2017.3 is deleted! 

Regards,
Farnam

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