cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
fabio_2998
Visitor
Visitor
805 Views
Registered: ‎11-27-2019

Process "Place & Route" failed with no errors or warnings

Jump to solution

Hi all,

I'm trying to generate a programming file for basys2 but the process fails to pass the "Place & Route" with no errors or warnings...

Here's the console log:


Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -pl high -rl high -t 1 -ntd main_map.ncd main.ncd main.pcf

 

Constraints file: main.pcf.
Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\12.4\ISE_DS\ISE\.
"main" is an NCD, version 3.2, device xc3s100e, package cp132, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)


Device speed data version: "PRODUCTION 1.27 2010-11-18".


Design Summary Report:

Number of External IOBs 4 out of 83 4%

Number of External Input IOBs 3

Number of External Input IBUFs 3
Number of LOCed External Input IBUFs 3 out of 3 100%


Number of External Output IOBs 1

Number of External Output IOBs 1
Number of LOCed External Output IOBs 1 out of 1 100%


Number of External Bidir IOBs 0


Number of BUFGMUXs 1 out of 24 4%


Overall effort level (-ol): Not applicable because -pl and -rl switches are used
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High


Starting Placer
Total REAL time at the beginning of Placer: 0 secs
Total CPU time at the beginning of Placer: 0 secs

Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:4ad4c7) REAL time: 0 secs

Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:4ad4c7) REAL time: 0 secs

Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:4ad4c7) REAL time: 0 secs

Phase 4.2 Initial Clock and IO Placement

Phase 4.2 Initial Clock and IO Placement (Checksum:78b5e7) REAL time: 0 secs

Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:78b5e7) REAL time: 0 secs

Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:78b5e7) REAL time: 0 secs

Phase 7.8 Global Placement
Phase 7.8 Global Placement (Checksum:78b5e7) REAL time: 0 secs

Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:78b5e7) REAL time: 0 secs

Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:78b5e7) REAL time: 0 secs

Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:78b5e7) REAL time: 0 secs

Total REAL time to Placer completion: 0 secs
Total CPU time to Placer completion: 0 secs
Writing design to file main.ncd

 

Starting Router


Phase 1 : 5 unrouted; REAL time: 0 secs

Phase 2 : 3 unrouted; REAL time: 0 secs

Phase 3 : 0 unrouted; REAL time: 0 secs

Phase 4 : 0 unrouted; REAL time: 0 secs

Total REAL time to Router completion: 0 secs
Total CPU time to Router completion: 0 secs

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| mclk_BUFGP | BUFGMUX_X2Y11| No | 1 | 0.000 | 0.053 |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs
Total CPU time to PAR completion: 0 secs

Peak Memory Usage: 4380 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file main.ncd

 

PAR done!

Process "Place & Route" failed

0 Kudos
1 Solution

Accepted Solutions
fabio_2998
Visitor
Visitor
596 Views
Registered: ‎11-27-2019

For those who want to know how I fixed it, I have reinstalled the xilinx ISE but this time with the 32 bit version and it worked even with my OS being 64bit.

View solution in original post

9 Replies
syedz
Moderator
Moderator
792 Views
Registered: ‎01-16-2013

@fabio_2998 

 

Can you try deleting the temp files and rerun the flow? From ISE, select Project --> Cleanup Project Files.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
fabio_2998
Visitor
Visitor
790 Views
Registered: ‎11-27-2019
Thanks for the fast reply, really thankfull for that but the solution didn't work at all. It keeps saying "Process "Place & Route" failed".
0 Kudos
drjohnsmith
Teacher
Teacher
782 Views
Registered: ‎07-09-2009

Can you post your code as an attachment please,
it looks like you have a clocked 2 input gate and one output , so should be small

BTW: what OS you running on ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
fabio_2998
Visitor
Visitor
772 Views
Registered: ‎11-27-2019

All the files are is this file .zip

I had followed a tutorial from my teacher and since there is no errors and warnings I'm assuming that I've copied it right, so can't figure it out why it's not working properly. I'm using windows 10 Pro 64B bit.

Thanks for showing interest in helping me :D

0 Kudos
drjohnsmith
Teacher
Teacher
759 Views
Registered: ‎07-09-2009
Well, thats your problem

ISE does does not run on windows 10,

There is a version that says windows 10, but it also says its only for spartan 6. and that runs under Linux on a VM under windows 10

You need to have windows 7 to run ISE 14.7.
that can either be a native windows 7 machine, or a windows 10 machine with your own VM with windows 7 / linux on depending upon your preference.

BTW: If your instructor is telling you to use clk' event and clk = '1'
point them at the forums to ask if they should...

use rising_edge( clk ) has been used for the last 20 years

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
fabio_2998
Visitor
Visitor
733 Views
Registered: ‎11-27-2019
I have a friend in my class that just did the same thing on a windows 10 computer with 12.4 version of Xilinx ISE as I did and it worked, that's why I'm asking for help.
0 Kudos
drjohnsmith
Teacher
Teacher
709 Views
Registered: ‎07-09-2009
Did not know about 12.4 working, interesting,

Silly question, does your ISE support your device ?
https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/irn.pdf

looks like your not using 14.7, but 12.4 also

"Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\12.4\ISE_DS\ISE\"

so it sounds like your machine,
Things like the path variable used to cause problems if it got past 250 odd characters,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
fabio_2998
Visitor
Visitor
597 Views
Registered: ‎11-27-2019

For those who want to know how I fixed it, I have reinstalled the xilinx ISE but this time with the 32 bit version and it worked even with my OS being 64bit.

View solution in original post

drjohnsmith
Teacher
Teacher
575 Views
Registered: ‎07-09-2009
well done for gettgin back

My guess was it was the re install that did it, not the 64/32 bit switch,

but its a great result either way
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos