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Observer tnjames
Observer
4,286 Views
Registered: ‎07-08-2013

Project-based partial reconfiguration with Vivado 2016.3 seems to ignore VHDL library info

Hi

 

I was interested to read that support for project-based partial reconfiguration has been added to Vivado 2016.3.  I have tried following the steps in UG909 to see if I could get it to work with an existing Zynq design that uses PR but unfortunately I got stuck quite quickly.

 

Our design files are split into VHDL libraries, with 'generic', reusable blocks in one library, board-support blocks in another and design-specific blocks in a third.  With the exception of black boxes, eg, the PR modules, and instantiated PL primitives we use explicit entity instantiation (rather than using separate component declarations, instantiations and use configurations) and in a non-PR project this works well, with Vivado showing the correct design hierarchy in the hierarchy view.  Unfortunately Vivado seems to ignore the library bindings for components added when defining new reconfiguration modules, which means that for each module I get a top level with black boxes for the low level entities and a bunch of 'unused' components.

 

If I go back into the 'edit reconfigurable module' dialog the listed entities are all associated with the xil_defaultlib library and although my libraries are listed if I select the correct libraries manually I cannot click 'ok'.  I've tried deleting the module and recreating double-checking that I have specified the correct library for each entity first time round and it still ignores the library specified and associates it with xil_defaultlib instead.

 

This is a shame as I like the idea of generating PR designs through the IDE but unless I'm missing something the current release is a bit broken.  (What would be really nice would be if I could add all of my files to the project, add the PR module top levels in the manner described in UG909 and have the tool automatically pull out the child modules from the existing modules already added to the project.)

 

Thanks in advance.

 

Tim

 

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4 Replies
Scholar austin
Scholar
4,281 Views
Registered: ‎02-27-2008

Re: Project-based partial reconfiguration with Vivado 2016.3 seems to ignore VHDL library info

Tim,

 

Are you using the ug909 revised and released for 2016.3?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer tnjames
Observer
4,271 Views
Registered: ‎07-08-2013

Re: Project-based partial reconfiguration with Vivado 2016.3 seems to ignore VHDL library info

Hi Austin

 

That was quick.  Yes, I'm looking at v2016.3, 5 October 2016, downloaded using DocNav.  The dialog in Figure 4-6 is where I have tried to change the library from xil_defaultlib.  In the partition definitions window, expanding my module hierarchy shows the first level of hierarchy below the root as black boxes as INST_LABEL - mylibname.mymodulename, with the missing modules shown (without children) at the same level as the root.

 

Tim

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Scholar austin
Scholar
4,262 Views
Registered: ‎02-27-2008

Re: Project-based partial reconfiguration with Vivado 2016.3 seems to ignore VHDL library info

Tim,

 

I will ping the responsible support person to look at your problem.  Stay tuned here for a response (may take a day or so).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer tnjames
Observer
3,524 Views
Registered: ‎07-08-2013

Re: Project-based partial reconfiguration with Vivado 2016.3 seems to ignore VHDL library info

Hi Austin

 

I don't know if you got a response on this but I note that the problem is still present in 2016.4.

 

Also, to clarify my last comment in my original post, what would be a useful enhancement is, if I add all my source files to my Vivado project as per a non-PR design (so I get multiple hierarchies shown, ie, my FPGA top level plus one or more 'PR hierarchies') then, having defined my 'partition definition' in the manner described in UG909, I could simply right-click on the 'PR hierarchies' displayed in the "Hierarchy" window and select "Create reconfigurable module" or similar to display a dialog from which I can select which partition this entity should be associated.  Once the PR partition top level is marked as such all of it's child modules (optionally in libraries other than work!) should be identified automatically.  (I note that there is already an option to go the other way, ie, you can already right-click files listed in the "Partition Definitions" window and select "Move to Design Sources".)

 

Best regards

 

Tim

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