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jhgf
Contributor
Contributor
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Registered: ‎09-24-2016

RAM64X1D internal architecture

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Hello,

 

I'm looking for a xilinx document showing the distributed ram (LUTRAM) RAM64X1D internal architecture. I'm curious to see how it is made.

I couldn't find any document online. Is this confidential?

Thank you,

 

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

i need to see the internal circuitry

I am pretty sure that if you look hard enough you can find the Xilinx patent for the SelectRAM - this was a major advantage that Xilinx had over Altera, and I am pretty sure that it was protected by patent.

But even without it, it's fairly easy to figure out what this is. Just ask yourself "What is a LUT?"

A LUT is a programmable function generator. Lets look at the older LUT4 (since it was a bit simpler). Any 4 input function can be represented by a truth table; for any of the 16 combinations of inputs, there is one output value. For a programmable LUT, this means that there are 16 programmable values that are then selected for the output. It is pretty clear that this is implemented with 16 storage elements (for holding the lookup values) and a 16:1 MUX for selecting the one you want based on the LUT inputs. This is a "programmable ROM". Really a programmable PROM, since the "ROM" lookup values are loaded into the LUT during the configuration phase (so we know these 16 storage elements are programmable).

To change this to a RAM, you just need to have a mechanism of dynamically changing the value in these 16 storage elements; i.e. you need to add write circuitry to them. This write circuitry is probably just a write enable on the storage cells and a 16:1 decoder. When you do so, you convert your LUT into a 16x1 single ported SRAM. Since the "read" side is still the LUT, it is an asynchronous read.

Since these are storage elements (and the read is combinatorial), they are actually readable and writeable at the same time. The only reason that (I think) a  single LUT is not dual-ported is that you don't have enough physical pins; a dual ported RAM needs to have an independent read address and write address. So if you combine two of them together, you get twice the pins (4 LUT inputs for the first LUT and 4 LUT inputs for the second) - this gives you enough pins for the read and write address.

Avrum

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dgisselq
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Registered: ‎05-21-2015

@jhgf,

Consider the distributed RAM chapter of the 7-series configurable logic block users's guide.

Dan

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jhgf
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Contributor
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Registered: ‎09-24-2016

But in this document there is nothing about the internal architecture. By internal architecture i mean is there a decoder inside the LUTRAM? if yes what else? It only shows obsolete boxes DPRAM and SPRAM, i need to see the internal circuitry 

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avrumw
Guide
Guide
497 Views
Registered: ‎01-23-2009

i need to see the internal circuitry

I am pretty sure that if you look hard enough you can find the Xilinx patent for the SelectRAM - this was a major advantage that Xilinx had over Altera, and I am pretty sure that it was protected by patent.

But even without it, it's fairly easy to figure out what this is. Just ask yourself "What is a LUT?"

A LUT is a programmable function generator. Lets look at the older LUT4 (since it was a bit simpler). Any 4 input function can be represented by a truth table; for any of the 16 combinations of inputs, there is one output value. For a programmable LUT, this means that there are 16 programmable values that are then selected for the output. It is pretty clear that this is implemented with 16 storage elements (for holding the lookup values) and a 16:1 MUX for selecting the one you want based on the LUT inputs. This is a "programmable ROM". Really a programmable PROM, since the "ROM" lookup values are loaded into the LUT during the configuration phase (so we know these 16 storage elements are programmable).

To change this to a RAM, you just need to have a mechanism of dynamically changing the value in these 16 storage elements; i.e. you need to add write circuitry to them. This write circuitry is probably just a write enable on the storage cells and a 16:1 decoder. When you do so, you convert your LUT into a 16x1 single ported SRAM. Since the "read" side is still the LUT, it is an asynchronous read.

Since these are storage elements (and the read is combinatorial), they are actually readable and writeable at the same time. The only reason that (I think) a  single LUT is not dual-ported is that you don't have enough physical pins; a dual ported RAM needs to have an independent read address and write address. So if you combine two of them together, you get twice the pins (4 LUT inputs for the first LUT and 4 LUT inputs for the second) - this gives you enough pins for the read and write address.

Avrum

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