RTSTAT10 No Routable Nets

[ajasan]

Hi 

I am craeting a bitfile for VU440 FPGA which has DDR4 MIG controller. Bitfile is successfully generated without timing violation. However I am getting a DRC warning as follows. 

I am yet to test the bitfile on board. But I am trying to understand what causes this DRC warning and if it will impact DDR4 MIG functionality.

Please share your suggestion.

Thanks,

Aj.

RTSTAT #1 Warning 168 net(s) have no routable loads. The problem bus(es) and/or net(s) are /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/LMB_CE_riu, /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/LMB_UE_riu, /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[12], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[13], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[14], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/Q[15], xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg[1], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[0].sync_reg[1], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[0].sync_reg[1], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg[1], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg[1], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[1].sync_reg[1], xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[1].sync_reg[1], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[1].sync_reg[1], /xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[2].sync_reg[1] (the first 15 of 168 listed).

[bruce_karaffa]

Is the IO of the MIG mapped to FPGA pins?  Does the IO of the MIG go through the top level of the design to the pads of the FPGA or is the MIG just instantiated and its IO just hang there?

[marcb]

Hi @ajasan 

The best way to find out what is happening is to trace some specific logic mentioned in the message at each stage of the Build flow.

Does the specific net have a load after synthesis when opening the design?

• If there is no load, verify the IP connections in the HDL instantiating the block. From selecting the cell in the post-synthesis schematic, you can right-click and select "Go to Source" to view the related source. Also verify the synthesized DCP for the particular IP (within <project_name>.runs/<IP_name>_synth/<IP_name>.dcp
• If there are loads after synthesis, add the verbose messaging to opt_design to see if logic is being removed, and why.

https://www.xilinx.com/support/answers/58616.html

[ajasan]

Thanks for the response @bruce_karaffa . Yes, pins are mapped to IO. They are not hanging.

[ajasan]

Thanks for the response @marcb .

This particular net on the message is shown n/c in Implemented design. I checked the RTL. It is driven 1'b0.

This is part of code inside DDR4 SDRAM MIG IP block. Please check the hierarchy as below, if it can give any hint.

$TOP/xilinx_ddr_if_inst/xilinx_ddr4_inst/inst/u_ddr4_mem_intfc/u_ddr_cal_riu

assign LMB_CE = 1'b0;

(* dont_touch = "true" *) output LMB_CE 

Thanks,

Aj.

[marcb · Accepted solution]

Hi @ajasan 

If the LMB_CE is not connect (n/c), then the warnig would make sense. 

The code snippet shows that it is driven, but does it have loads, or connect to any leaf primitive? I would check this from the open implemented design.

[ajasan]

Its an undriven load and it works fine on board. So I guess the Warning is safe to ignore.

Thank you for the response!

Thanks,

Aj.