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Anusua
Observer
Observer
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Registered: ‎06-18-2020

Reducing the LUT ultilization for Zynq Ultrascale+

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I want to reduce the resource utilization on Zynq Ultrascale+, LUT utilization for my design is 91%. The whole design is mostly consisting of Xilinx IP cores(3G SDI video-audio). Most part of the design is implemented as block design, although not by using auto-generated wrapper. Is there any possibility to convert LUT memory to BRAM? Or any other idea as to reduce the LUT counts? I have gone through the different implementation strategies (Area_Explore) however, does not reduce LUT count at all, instead sometimes increased the count. Tool: Vivado 2019.1

Any other ideas in this direction is also appreciated. Thanks!

 

 

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

use a bigger part 

BRAM memory is either infered or instantiated, 

    to infer as it sounds you are trying to do, you need a template that the tools understand, and the design must use the BRAMs in a way they support,

        i.e. registered, 

I'd guess the IP is already using BRAM where it can.

 

 

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drjohnsmith
Teacher
Teacher
395 Views
Registered: ‎07-09-2009

use a bigger part 

BRAM memory is either infered or instantiated, 

    to infer as it sounds you are trying to do, you need a template that the tools understand, and the design must use the BRAMs in a way they support,

        i.e. registered, 

I'd guess the IP is already using BRAM where it can.

 

 

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Anusua
Observer
Observer
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Registered: ‎06-18-2020

Is there any way to convert some LUTs inside the IP cores into LUTRAM or Block RAM?

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watari
Professor
Professor
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Registered: ‎06-16-2013

Hi @Anusua 

 

What kind of IPs are you using ?

Also, did you make sure ex.  the value of C_USE_URAM property at ex. VPSS ?

And, did you make sure the result of "report_ram_utilization" and "report_utilization" command ?

 

Best regards,

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Anusua
Observer
Observer
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Registered: ‎06-18-2020

@watari 

I am using IPs like SMPTE UHD-SDI RX, TX, RX brifge, Video Timing Controller, Video-In-To AXI4 Stream; 10G Ethernet subsystem, & so on. But I don't use VPSS in my design. Yes, some of the IP cores infer the BRAM, LUTRAM but my question, is since, these are utilized very less in the resources, and the LUT counts are huge, is there a possibility to implement some of the logic inside the IP core as LUTRAM or BRAM.

The report_ram_utilization command gives the summary of the RAM usage used by the cores in my design.

1. Summary
----------

+--------------------------+------------+-----------+--------+------------+
| Memory Type | Total Used | Available | Util % | Inferred % |
+--------------------------+------------+-----------+--------+------------+
| URAM | 6.0 | 48 | 12.5 | 100.0 |
| URAM288 | 6 | | | 100.0 |
| BlockRAM | 59.0 | 128 | 46.1 | 100.0 |
| RAMB36E2 | 45 | | | 100.0 |
| RAMB18E2 | 28 | | | 100.0 |
| LUTMs as Distributed RAM | 338.0 | 57600 | 0.6 | 89.9 |
| LUTMs as RAM64X1S | 2 | | | 0.0 |
| LUTMs as RAM64X1D | 2 | | | 0.0 |
| LUTMs as RAM64M8 | 65 | | | 96.9 |
| LUTMs as RAM32X1D | 1 | | | 0.0 |
| LUTMs as RAM32M16 | 241 | | | 100.0 |
| LUTMs as RAM32M | 27 | | | 0.0 |
+--------------------------+------------+-----------+--------+------------+
* Each RAMB18 is calculated as 0.5 BlockRAM
** Detailed reports below cover XPMs and Vivado Synthesis inference for BlockRAMs and URAMs only

 

And I am check the total resource utilization via the report utilization command.

And what is meant by "did you make sure ex. the value of C_USE_URAM property at ex. VPSS"? Something you mean using HLS? Or what to do with it?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

I would hope the IP has been optimised already ...

 

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