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Registered: ‎08-23-2011

Reg: Board usage and amount of free space left on FPGA ...



I had some rather large designs which I was able to imlpement on the FPGA, but from the design summary, I was not able ot figure out how much free space is left on the FPGA fabric. The device utilization is below. I can understand utilization such as that of primitives, feature utilization, i/o utilization. But For the FPGA fabric itself, which metric gives the best estimate of the amount of space used up/free on the FPGA? Is it slice regs used, slice luts used or no. of slices occupied?


Also, at what %utilization, is it a good idea to start breaking up the FPGA code and distributing it on 2 FPGAs (master-slave type of arrangement)?


Thanks and regards,

Zubin Kumar.


Slice Logic Utilization:
Number of Slice Registers: 20,413 out of 32,640 62%
Number used as Flip Flops: 20,381
Number used as Latches: 32

Number of Slice LUTs: 22,036 out of 32,640 67%
Number used as logic: 20,868 out of 32,640 63%
Number using O6 output only: 15,718
Number using O5 output only: 1,596
Number using O5 and O6: 3,554

Number used as Memory: 161 out of 12,480 1%
Number used as Shift Register: 161
Number using O6 output only: 160
Number using O5 output only: 1
Number used as exclusive route-thru: 1,007
Number of route-thrus: 3,000 out of 65,280 4%
Number using O6 output only: 1,742
Number using O5 output only: 402
Number using O5 and O6: 856


Slice Logic Distribution:
Number of occupied Slices: 7,558 out of 8,160 92%
Number of LUT Flip Flop pairs used: 27,130
Number with an unused Flip Flop: 6,717 out of 27,130 24%
Number with an unused LUT: 5,094 out of 27,130 18%
Number of fully used LUT-FF pairs: 15,319 out of 27,130 56%
Number of unique control sets: 731
Number of slice register sites lost
to control set restrictions: 1,342 out of 32,640 4%


IO Utilization:
Number of bonded IOBs: 361 out of 480 75%


Specific Feature Utilization:
Number of BlockRAM/FIFO: 120 out of 132 90%
Number using BlockRAM only: 120

Total primitives used:
Number of 36k BlockRAM used: 107
Number of 18k BlockRAM used: 25
Total Memory used (KB): 4,302 out of 4,752 90%
Number of BUFG/BUFGCTRLs: 6 out of 32 18%
Number used as BUFGs: 6
Number of DCM_ADVs: 2 out of 12 16%
Number of DSP48Es: 77 out of 288 26%

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3 Replies
Registered: ‎09-09-2010

This is NOTHING to do with "board usage". If you don't know a board from an IC...

You are using 62% of the registers, 67% of the LUTs, 90% of the RAM, 26% of the DSPs, and not much else. BlockRAM usage is therefore the important figure for you.

Can't say much more without knowing wahat family you are using.

"If it don't work in simulation, it won't work on the board."
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Registered: ‎08-23-2011

The FPGA I am using is Xilinx Virtex5 XC5VSX50T.

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Registered: ‎08-14-2007

While block RAM is the highest percentage, it is perfectly reasonable to use 100% of block RAM

resources (given you don't expect to expand the design).  However it is very hard to use 100% of

the fabric LUTs or registers without running into problems.  As you can see, although the larger

of the two is only 67%, you are at least partially using 92% of the slices.  As you start to add more

logic, more of the slices will be fully utilized, and more slices will thus have some unrelated

logic packed together.  This eventually makes placement and routing very hard, especially if

you need to meet aggressive timing constraints.  67% of LUTs or flip-flops in a large Virtex 5

is probably a good place to start thinking about partitioning the design.  Note that in a smaller

FPGA, this percentage may be larger because you don't have as large a possible routing

distance in a smaller fabric.  Very low density FPGA's can be used very close to 100%.


The Virtex 5 SX50T is probably good up to somewhere between 70-75% LUTs or registers

before you need to spend a lot of time on timing closure.


-- Gabor

-- Gabor