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Newbie
Newbie
320 Views
Registered: ‎04-25-2019

Regarding Vivado XDC file

I have used the following lines in XDC file:

1. set_property LOC GTXE2_CHANNEL_X0Y6 [get_cells Inst_PCIE_EP/pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i]

2. set_property LOC GTXE2_CHANNEL_X0Y7 [get_cells Inst_PCIE_EP/pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i]

3.set_property LOC PCIE_X0Y0 [get_cells Inst_PCIE_EP/pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i] 

The bit file will get generate. But the following critical warnings appear for the above lines:

pic2.png

 

 

 

 

 

The hardware used: Kintex 7 -> xc7k325tffg676-1

Please provide the solution. Thank you.

 

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Xilinx Employee
Xilinx Employee
310 Views
Registered: ‎05-22-2018

Hi @meg36 ,

Please check this AR# link:

https://www.xilinx.com/support/answers/56169.html

Thanks,

Raj

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