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Observer sabiya
Observer
362 Views
Registered: ‎07-26-2019

Route design error

Hi,

I implemented a display port transmitter on xczu9eg-ffvc900-1-e (active) board part. I got below error in buffers.

Screenshot from 2019-09-20 15-18-20.png
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3 Replies
Observer sabiya
Observer
336 Views
Registered: ‎07-26-2019

Re: Route design error

please help me. I got a error in differential clock.

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Teacher drjohnsmith
Teacher
313 Views
Registered: ‎07-09-2009

Re: Route design error

have you gone through this

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug949-vivado-design-methodology.pdf

 

From what you have showen us, you have some IO pins in the desgn that you XDC has mapped to pins that do not exist / or can not support the standard or function you intend.

Look in the tcl window to see where the first error is .

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
228 Views
Registered: ‎05-22-2018

Re: Route design error

Hi @sabiya ,

Try routing the failing nets manually by using route_design -nets command and see if it is able to route. 

route_design -nets [get_nets dp_tx/display_tx_/util_ds_buf_1/U0/IBUF_OUT[0]]

Thanks,

Raj

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