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Observer
Observer
623 Views
Registered: ‎07-16-2019

Routing error if ILA added at MIPI CSI input

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Hi,

I have a design with a MIPI CSI-2 Rx Subsystem (4.0) core where the bitstream can already be successfully generated.
If I add an ILA to the input MIPI CSI data pins, I get errors at DRC because of a routing error:

These are the messages:

Implementation Critical Warnings:
[Route 35-54] Net: mipi_phy_if_0_data_p[1] is not completely routed.
[Route 35-7] Design has 4 unroutable pins, potentially caused by placement issues.
[Route 35-1] Design is not completely routed. There are 4 nets that are not completely routed.

DRC Error:
[DRC RTSTAT-2] Partially routed nets: 4 net(s) are partially routed. The problem bus(es) and/or net(s) are mipi_phy_if_0_data_n[1:0], and mipi_phy_if_0_data_p[1:0].

report_route_status:
Nets with Routing Errors:
mipi_phy_if_0_data_n[0]
Unrouted Pin: u_ila_0/inst/PROBE_PIPE.shift_probes_reg[0][0]/D
mipi_phy_if_0_data_n[1]
Unrouted Pin: u_ila_0/inst/PROBE_PIPE.shift_probes_reg[0][1]/D
mipi_phy_if_0_data_p[0]
Unrouted Pin: u_ila_0/inst/PROBE_PIPE.shift_probes_reg[0][2]/D
mipi_phy_if_0_data_p[1]
Unrouted Pin: u_ila_0/inst/PROBE_PIPE.shift_probes_reg[0][3]/D

I'm using as clock domain for the ILA the video_aclk (250 Mhz, fabric clk3). I also tried to use the dphy_clk_200M (200Mhz, fabric clk2) but there is no difference.

There is a similar question but I can't solve mine issue with this:
https://forums.xilinx.com/t5/Implementation/Error-1-signals-are-not-completely-routed/td-p/661634

I attached the rtp files ofthe implementation like at the mentioned question. The system_top_routed.dcp file is for upload too big, also after zipping it is 40MB.

Is it possible to use ILA at the MIPI CSI-2 input? I want to use it clock and data lanes.

Thanks,
Christoph

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Moderator
Moderator
512 Views
Registered: ‎11-09-2015

Hi @chehre1 

What you are trying to do will not work as there is only a single path. So you will not be able to route both the ILA and the actual MIPI output.

The only way you can capture the mipi signal output is by using an external scope.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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3 Replies
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Xilinx Employee
Xilinx Employee
610 Views
Registered: ‎05-22-2018

Hi @chehre1 ,

Open Implemented design and check the below

 

1. Is the connectivity of the failing net correct? 

2. What is the source and load? Where are they placed?

Also check this AR#:

https://www.xilinx.com/support/answers/53854.html

Thanks,

Raj

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Observer
Observer
518 Views
Registered: ‎07-16-2019

Hi @rshekhaw ,

I followed the answer record and got now some additional information but not that much.
I examined the partial routed nets in the Device Editor, which are the connections listed in my first question. If I click on the first net mipi_phy_if_0_data_n[0] and click on "Route", there is additional information printed in the console about driver and load. I attached this in the Route_mipi_phy_if_0_data_n[0].txt.

I don't really understand the common issues to look for in the answer record. 

1. Is the connectivity of the failing net correct? 

I think so, I checked the schematic of the first net. See the attachment Schematic_Connection_mipi_phy_if_0_data_n[0].PNG.

Is there a other way to check it?

2. What is the source and load? Where are they placed?

I am not sure how to look for source and load. I hope that this is explained in the .txt with driver and load. 
For the placement I highlighted and marked the connection in the device view, see Device_Connection_mipi_phy_if_0_data_n[0].PNG.

  • There you can see the pad in the mipi_phy_if_0_data_n[0] middle.
  • The right cell is IBUFDS_DPHY: i_system/mipi_csi2_rx_subsyst_0/U0/phy/inst/inst/bd_2c7a_0_phy_0_rx_support_i/slave_rx.bd_2c7a_0_phy_0_rx_hssio_i/inst/top_inst/iobuf_top_inst/io_gen[36].ibufds_dphy.
  • The upper left is LUT3: u_ila_0/inst/ila_core_inst/probeDelay1[0]_i_1.
  • The lower left is SRL16E: u_ila_0/inst/ila_core_inst/shifted_data_in_reg[7][0]_srl8.

Is there a other way to check source/load and placement?

Thanks for you answer. I'm not that skilled in debugging designs.

Best regards,
Christoph

Schematic_Connection_mipi_phy_if_0_data_n[0].PNG
Device_Connection_mipi_phy_if_0_data_n[0].PNG
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Highlighted
Moderator
Moderator
513 Views
Registered: ‎11-09-2015

Hi @chehre1 

What you are trying to do will not work as there is only a single path. So you will not be able to route both the ILA and the actual MIPI output.

The only way you can capture the mipi signal output is by using an external scope.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post