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helmutforren
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Registered: ‎06-23-2014

Rule violation (BIVC-1) Bank IO standard Vcc

I don't understand why I'm getting the following error, 

 

ERROR: [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs:  
ddr3_1_p[0] (DIFF_HSTL_II_18, requiring VCCO=1.800) and RESET (LVCMOS15, requiring VCCO=1.500)

because the xdc file constraints ddr3_1_p[0] with:

set_property PACKAGE_PIN AF11 [get_ports {ddr3_1_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_1_p[0]}]   // HgF - Changed from SSTL15 to DIFF_SSTL15

Isn't this saying "DIFF_SSTL15"?  I don't see why the error complained or how it came up with DIFF_HSTL_II_18.

 

Any ideas?  I'll attach the whole xdc.

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helmutforren
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Registered: ‎06-23-2014

Now I switched to a KC705 xdc file, changed some names, and STILL get errors I can't figure out.  Here's the alternative attempt

ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 4 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: FMC_LPC_LA12_N, FMC_LPC_LA12_P, SYSCLK_P, SYSCLK_N.
ERROR: [DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal Artemis/CL_CLK_PLL/inst/clk_in1 on the Artemis/CL_CLK_PLL/inst/plle2_adv_inst/CLKIN1 pin of Artemis/CL_CLK_PLL/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: SYSCLK_P, SYSCLK_N.

Attached xdc.

 

Here's my top level module:

module Top(
        input SYSCLK_P,
        input SYSCLK_N,
        input CPU_RESET,
        input GPIO_DIP_SW0,
        output FMC_LPC_LA12_P,            // output clock
        output FMC_LPC_LA12_N             // output clock
    );
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balkris
Xilinx Employee
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Registered: ‎08-01-2008

Try these steps:
1. Open Implemented design
2. Select IO ports tab in the bottom of Vivado GUI (i.e., tab beside Tcl console)
3. Now make sure whether you had specified I/O Standard for all the IOs in the design.

 

You can also open implemented design, change the layout to I/O planning, and look at the I/O ports window to see if LVDS_18 is applied to the problem ports.

 

impl_std.png

 

If not applied, then the sdc constraint is not read in.

 

I suggest that you define them in XDC instead.

e.g.

set_property PACKAGE_PIN AD41 [get_ports mb_rclk_100mhz_p]
set_property PACKAGE_PIN AE41 [get_ports mb_rclk_100mhz_n]

set_property IOSTANDARD LVDS_18 [get_ports mb_rclk_100mhz_p]
set_property IOSTANDARD LVDS_18 [get_ports mb_rclk_100mhz_n]

 

Thanks and Regards
Balkrishan
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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @helmutforren

 

Which version of vivado are you using?

 

Can you share MIG IP XCI file?

Thanks,
Deepika.
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tonykaravidas
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Registered: ‎02-04-2008

I'm having a similar issue as the OP. 

My message is:

 

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 14. For example, the following two ports in this bank have conflicting VCCOs:  MCLK3 (LVCMOS18, requiring VCCO=1.800) and SDTO8 (LVCMOS33, requiring VCCO=3.300)

 

I'm not sure how it's getting  a standard of LVCMOS18 for MCLK3, since I have this in my constraint file:

set_property IOSTANDARD LVCMOS33 [get_ports MCLK3]
set_property PACKAGE_PIN P18 [get_ports MCLK3]

 

Also, I can't open implemented design because it's failing during implementation.

 

 

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tonykaravidas
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Registered: ‎02-04-2008

If I remove the checkbox to use the XDC file during implementation, it will complete implementation.

So, I'm now looking at the I/O ports as shown in the screen shot, and it's defaulting many of my pins to LVCMOS18.

I have them ALL defined in the XDC file as LVCMOS33:

 

set_property IOSTANDARD LVCMOS33 [get_ports BCLK]
set_property PACKAGE_PIN M14 [get_ports BCLK]
set_property IOSTANDARD LVCMOS33 [get_ports LRCLK]
set_property PACKAGE_PIN N17 [get_ports LRCLK]

 

Why does it think the default is 1.8V, and how can I change it??

Screenshot 2017-07-28 12.44.23.png
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