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Explorer
Explorer
7,006 Views
Registered: ‎05-15-2009

Same project, different map results

I wrote some weekes ago about some problems with IOSTANDARD

 

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Problem-with-IOSTANDARD/m-p/165314

 

I tried to see where's the problem so, today, I have been able to use my work associate's personal computer, with Xilinx ISE 12.1 installed.

 

I want to remark that we have

 

-same OS (Windows 7)

-same Xilinx ISE (12.1)

-same tools or similar installed

 

I tried to compile the SAME PROJECT, put inside the same folder on desktop, so it doesen't depend on project folder position

 

The very strange things is that, the SAME project, with my Xilinx ISE 12.1 show me the famous message

 

LIT:600 - IOBUFDS symbol "u_ddr2_top/u_ddr2_top_rx/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2_ddr3.u_iobuf_dqs" (output signal=u_ddr2_top/u_ddr2_top_rx/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/dqs_ibuf) does not have IOSTANDARD specified. Map is unable to generate a default IOSTANDARD for IOBUFDS, one has to be explicitly provided.

 

an in the other one instead everything is good!!!

How is it possible???

 

IOSTANDARD attributes are added everywhere is needed

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6 Replies
Teacher eteam00
Teacher
7,001 Views
Registered: ‎07-21-2009

Re: Same project, different map results

Have you opened a webcase?  If not, perhaps it's a good idea.  When you resolve this problem, please post the solution to the forum thread so we can all learn from your troubles.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
6,999 Views
Registered: ‎07-01-2008

Re: Same project, different map results

It sounds as though you have copied the project to the local desktop. Make sure that you are running NGDBuild without timestamp dependancy since the copy wil have reset the timestamps. You might have an out of date file that is not being recognized as such.

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Visitor mlaffin
Visitor
6,894 Views
Registered: ‎02-07-2012

Re: Same project, different map results

Had the same or a similar problem.

Removed the relevant UCF from the project and then added it back into the project.

The suggested to alter time stamp settings did not fix problem; nor did cleaning up project files.

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Scholar golson
Scholar
6,054 Views
Registered: ‎04-07-2008

Re: Same project, different map results

Thank you for this advice.  I also removed the UCF file and added it back in to the project. And the error did go away for me also.

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Newbie maaz90
Newbie
6,037 Views
Registered: ‎09-03-2013

*Off topic* need help regarding udp echo lwip

greetings sir golson,

i ve been following your activity on the xilinx forums regarding lwip echo server and relevant data,i need your help,if you can share your facebook or gmail contact details with me,i would like to share my current project that i am working on,how much i ve already achieved and how do i plan to reach my goal and then further on optimize my project,for a start its based on udp echo server,and i ve implemented the hardware desing using MHS file in the xapp1026 reference design for xilinx 14.3 ISE design suite,

really looking forward to your earliest reply,sharing my experiences with your and learning from you...

regards

maaz

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Highlighted
Adventurer
Adventurer
2,747 Views
Registered: ‎05-24-2013

Re: Same project, different map results

Hello bwade,

 

I also have the same problem. Same project has two different PAR results. One has timing closure, the other one does not complete the routing task. The only difference between the two projects is that I have put them to different folders. However there are no absolute paths in the project also the XST yields identical results (I checked the Design summary section of th .syr report). Also the checksums are identical up to Global Placement.

 

I also followed your suggestion with Netlist Translation Type in Translate. The value "On" did not help unfortunately.

 

Is there a way to check the timestamp values of the ngc files? Do you have other suggestions?

 

Thanks,

Berk

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