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Contributor
Contributor
1,044 Views
Registered: ‎10-09-2017

[Shape builder 18-119] Failed to create I/O LOGIC Route through shape for instance design_testjig_wrapper_inst/design_testjig_i/axi_ethernet_1/inst/eth_mac/inst/rgmii_interface/rgmii_rx_ctl_ibuf_i

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Hi All,

I am getting a critical warning for the Ethernet instances.

 

[Shape Builder 18-119] Failed to create I/OLOGIC Route Through shape for instance design_testjig_wrapper_inst/design_testjig_i/axi_ethernet_1/inst/eth_mac/inst/rgmii_interface/rgmii_rx_ctl_ibuf_i. Found overlapping instances within the shape: design_testjig_wrapper_inst/design_testjig_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i and design_testjig_wrapper_inst/design_testjig_i/axi_ethernet_1/inst/eth_mac/inst/rgmii_interface/rgmii_rx_ctl_ibuf_i.

 

my design has two 1G/2.5G Ethernet subsytem,where one is included shared logic in core and second one is included shared logic in example design.please find the attached snapshot of the design below.

 

Please help me to understand why i am getting this warning and How can i solve this.

 

Thank You.

Design_ethernet.png
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Xilinx Employee
Xilinx Employee
1,179 Views
Registered: ‎05-08-2012

Re: [Shape builder 18-119] Failed to create I/O LOGIC Route through shape for instance design_testjig_wrapper_inst/design_testjig_i/axi_ethernet_1/inst/eth_mac/inst/rgmii_interface/rgmii_rx_ctl_ibuf_i

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Hi @poornima_95. Is the target part a 7-Series device? The message looks to indicate so, but I wanted to confirm. Also, can you indicate what type of primitives the two instances in the message are?

 

A shape is an internally generated relatively placed macro that is intended to assist place_design. IO instances would need to have the correct relative coordinates. This message would indicate that there is overlap within the shape. I would try checking if the two cores have conflicting IO constraints.

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Xilinx Employee
Xilinx Employee
1,180 Views
Registered: ‎05-08-2012

Re: [Shape builder 18-119] Failed to create I/O LOGIC Route through shape for instance design_testjig_wrapper_inst/design_testjig_i/axi_ethernet_1/inst/eth_mac/inst/rgmii_interface/rgmii_rx_ctl_ibuf_i

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Hi @poornima_95. Is the target part a 7-Series device? The message looks to indicate so, but I wanted to confirm. Also, can you indicate what type of primitives the two instances in the message are?

 

A shape is an internally generated relatively placed macro that is intended to assist place_design. IO instances would need to have the correct relative coordinates. This message would indicate that there is overlap within the shape. I would try checking if the two cores have conflicting IO constraints.

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Contributor
Contributor
884 Views
Registered: ‎10-09-2017

Re: [Shape builder 18-119] Failed to create I/O LOGIC Route through shape for instance design_testjig_wrapper_inst/design_testjig_i/axi_ethernet_1/inst/eth_mac/inst/rgmii_interface/rgmii_rx_ctl_ibuf_i

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Hi@marcb ,

Thank you for your reply. I have already solved this warning, as you said it was because of the conflicting IO constraints. the two rx_clk buffers were overlapping.

 and yes the target is 7 series device.

 

 

 

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