02-06-2019 01:50 PM
Vivado 2018.2, added an utility:OR gate.
And trying a new implementation run, it takes about the same amount of time to have a whole compile.
Is this normal?
02-06-2019 02:10 PM
If you made a change and didn't specify an Incremental Compile using an existing Design Checkpoint file:
then you essentially did a whole compile. So: Yeah; it should have taken about the same amount of time as a "whole compile."
02-06-2019 02:14 PM
What I did select in Incremental compile is: *_top_routed.dcp.
But I changed small thing inside the block design. Still runs like compile all. Is this normal?
02-06-2019 02:39 PM
With any logic change, the process still needs to go through Synthesis. If you're building in Out Of Context per IP mode, then that should be a minimal delay--compared to globally re-synthesizing the whole design. Any benefit will come later, in the Implementation phase.
Sadly, nothing involving FPGA implementation seems 'fast' these days. It could take several minutes just to throw a simple gate into an otherwise empty FPGA and build only that. Incremental Compile will shorten a large or difficult design from a really, really long implemenation time to just a long implementation time. (I assumed that's what you have, since you're trying alternate Implementation strategies.) A simple design is still going to take a relatively 'long' time, whether you're doing Incremental Compile or not.
P.S. And don't ask me why Writing Bitstream can take 4-5 minutes. I capitulated to that mystery long ago.
02-07-2019 01:18 AM
What is the % resue in report_incremental_resue command? If your reference checkpoint was timing closed and If the new changes are violating timing then the tool will try to fix the new timing violation at expense of runtime.
If you can share the design then we can check or else share the vivado.log file of the default run and with the incremental run.