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shantmoses
Contributor
Contributor
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Registered: ‎07-01-2008

Spartan-6 LX25T BUFIO2 clocking regions

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Hi all,

 

I'm getting the following errors when trying to build a Spartan-6 LX25T FGG484 logic that uses BUFIO2 clocks and OSERDES components in a transmitter interface.

 

ERROR:Place:1171 - The BUFIO instance <inst_p2s_intf/inst_phy/bufio2_inst> needs
to have all of its IOB loads placed into its same half IO bank. However, the
user has locked it to site <BUFIO2_X0Y16>, and locked its IOB load
<p2s_pdata<0>> to site <PAD239>, which is in a different half IO bank. Please
check user-specified LOCATION constraints and make sure they do not violate
this rule.
ERROR:Place:1171 - The BUFIO instance <inst_p2s_intf/inst_phy/bufio2_inst> needs
to have all of its IOB loads placed into its same half IO bank. However, the
user has locked it to site <BUFIO2_X0Y16>, and locked its IOB load
<p2s_pdata<1>> to site <PAD240>, which is in a different half IO bank. Please
check user-specified LOCATION constraints and make sure they do not violate
this rule.

 

The clock and data pins are located at the following pins:

 

NET "p2s_pclk_p" LOC = M5 | IOSTANDARD = LVPECL_33; # Bank 3 GCLK23
NET "p2s_pclk_n" LOC = M4 | IOSTANDARD = LVPECL_33; # Bank 3 GCLK22
NET "p2s_pdata[0]" LOC = M6 | IOSTANDARD = LVTTL;
NET "p2s_pdata[1]" LOC = L6 | IOSTANDARD = LVTTL;
NET "p2s_pdata[2]" LOC = K6 | IOSTANDARD = LVTTL;
NET "p2s_pdata[3]" LOC = K5 | IOSTANDARD = LVTTL;
NET "p2s_pdata[4]" LOC = K4 | IOSTANDARD = LVTTL;
NET "p2s_pdata[5]" LOC = K3 | IOSTANDARD = LVTTL;
NET "p2s_pdata[6]" LOC = K2 | IOSTANDARD = LVTTL;
NET "p2s_pdata[7]" LOC = K1 | IOSTANDARD = LVTTL;

 

UG385 document indicates that all the clock and data lines are located in BUFIO2 clock region "LT" but the package file linked below marks the clock pins as they're located in an "LB" region with a comment to an "LT" physical location.

 

http://www.xilinx.com/support/packagefiles/s6packages/6slx25tfgg484pkg.txt

 

 

M5	3	LB	IO_L43P_GCLK23_M3RASN_3		// Physical location is LT 
M4	3	LB	IO_L43N_GCLK22_IRDY2_M3CASN_3	// Physical location is LT 
M3	3	LB	IO_L44P_GCLK21_M3A5_3		// Physical location is LT 
L4	3	LB	IO_L44N_GCLK20_M3A6_3		// Physical location is LT 
M6	3	LB	IO_L45P_M3A3_3		// Physical location is LT 
L6	3	LB	IO_L45N_M3ODT_3		// Physical location is LT 

 

In the same logic, there is a receiver logic interface that uses BUFIO2 clocks and ISERDES components to capture data. The clock and data pins for this interface are located at the following pins:

 

NET "s2p_pclk_p" LOC = M3 | IOSTANDARD = LVPECL_33; # Bank 3 GCLK21
NET "s2p_pclk_n" LOC = L4 | IOSTANDARD = LVPECL_33; # Bank 3 GCLK20
NET "s2p_pdata_p[0]" LOC = C1 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[0]" LOC = B1 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_p[1]" LOC = D2 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[1]" LOC = D1 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_p[2]" LOC = E3 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[2]" LOC = E1 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_p[3]" LOC = F3 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[3]" LOC = E4 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_p[4]" LOC = F2 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[4]" LOC = F1 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_p[5]" LOC = G3 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[5]" LOC = G1 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_p[6]" LOC = H2 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[6]" LOC = H1 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_p[7]" LOC = J3 | IOSTANDARD = LVPECL_33;
NET "s2p_pdata_n[7]" LOC = J1 | IOSTANDARD = LVPECL_33;

 

According to the package file, the clock is placed in an "LB" BUFIO2 region whereas the rest of the data bus is placed in an "LT" clocking region. Only the transmitter logic interface is failing the build in the placer phase.

 

Any help how to solve this problem? and why are these pins marked as being in an "LB" region but physically in "LT" region?

 

 

Thanks in advance,

Shant

 

 

 
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Accepted Solutions
shantmoses
Contributor
Contributor
16,391 Views
Registered: ‎07-01-2008

Hi there,

 

After carefully reviewing the Spartan-6 FPGA clocking resources UG382 document, I found out the difference in the LX25T BUFIO2 clocking region assignment from other devices in Figure1-10 page27.

 

Eventhough the interface clock (GCLK23 and GCLK22) is marked as being in an "LB" clocking region, its BUFIO2 IOCLK clocks logic in the "LT" clocking region.

 

Two data interface pins (M6 & L6) turned out to be located in an "LB" region, and thus not reachable by the IOCLK from the BUFIO2 leading to logic build failure with a confusing message indicating the bad pin assignment on a different data pin. After moving the signals connected to the (M6 & L6) pins into other pins in the "LT" region, I got the logic to build.

 

Regards,

Shant

 

 

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2 Replies
ashishd
Xilinx Employee
Xilinx Employee
9,535 Views
Registered: ‎02-14-2014
Hello,

Please check the below threads where similar issue is discussed
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/HELP-Problems-with-a-deserializer-wich-follow-xapp1064-in/td-p/203683
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Clocking-regions-in-XC6SLX25-FTG256/td-p/232373
Regards,
Ashish
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shantmoses
Contributor
Contributor
16,392 Views
Registered: ‎07-01-2008

Hi there,

 

After carefully reviewing the Spartan-6 FPGA clocking resources UG382 document, I found out the difference in the LX25T BUFIO2 clocking region assignment from other devices in Figure1-10 page27.

 

Eventhough the interface clock (GCLK23 and GCLK22) is marked as being in an "LB" clocking region, its BUFIO2 IOCLK clocks logic in the "LT" clocking region.

 

Two data interface pins (M6 & L6) turned out to be located in an "LB" region, and thus not reachable by the IOCLK from the BUFIO2 leading to logic build failure with a confusing message indicating the bad pin assignment on a different data pin. After moving the signals connected to the (M6 & L6) pins into other pins in the "LT" region, I got the logic to build.

 

Regards,

Shant

 

 

View solution in original post

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