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Visitor dcw15
Visitor
334 Views
Registered: ‎02-28-2019

Still getting RTSTAT-2 violation after using "Fix Routes" Option

Hello,

 

I'm trying to add debug to a build which I already know builds fine and works on hardware, but when trying to finalise a build with debug in i get the following error:

[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 3 net(s) are partially routed. The problem bus(es) and/or net(s) are cmd_sts_if/Top_cmd/tx/sts_tx_out/sts_oserdes/clk_out, cmd_sts_if/Top_cmd/tx/sts_tx_out/sts_oserdes/U_1/data_out0, cmd_sts_if/Top_cmd/tx/sts_tx_out/sts_oserdes/U_1/data_out1.

I have tried opening the implemented design and using the "Fix Routes" option on the 3 nets listed. It shows that the original net is already routed, but those going to the debug core are not, so i select both and hit ok. Within my xdc file the following lines have been added:

 

set_property BEL D6LUT [get_cells {u_ila_1/inst/ila_core_inst/probeDelay1[0]_i_1__2}]
set_property BEL B6LUT [get_cells {u_ila_1/inst/ila_core_inst/shifted_data_in_reg[7][17]_srl8}]
set_property LOC SLICE_X95Y71 [get_cells {u_ila_1/inst/ila_core_inst/probeDelay1[0]_i_1__2}]
set_property LOC SLICE_X95Y54 [get_cells {u_ila_1/inst/ila_core_inst/shifted_data_in_reg[7][17]_srl8}]
set_property FIXED_ROUTE { { XIPHY_BITSLICE_TILE_291_TX_Q HPIO_IOB_31_OP_PIN HPIO_IOB_31_O_B HPIO_LVDS_OBUF_33_O_B_PIN }  } [get_nets cmd_sts_if/Top_cmd/tx/sts_tx_out/sts_oserdes/U_1/data_out0]
set_property FIXED_ROUTE { { XIPHY_BITSLICE_TILE_246_TX_Q HPIO_IOB_39_OP_PIN HPIO_IOB_39_O_B HPIO_LVDS_OBUF_41_O_B_PIN }  } [get_nets cmd_sts_if/Top_cmd/tx/sts_tx_out/sts_oserdes/clk_out]
set_property FIXED_ROUTE { { XIPHY_BITSLICE_TILE_193_TX_Q HPIO_IOB_23_OP_PIN HPIO_IOB_23_O_B HPIO_LVDS_OBUF_25_O_B_PIN }  } [get_nets cmd_sts_if/Top_cmd/tx/sts_tx_out/sts_oserdes/U_1/data_out1]

Trying another build i get the same error as before and am struggling to see where I am going wrong. 

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4 Replies
Xilinx Employee
Xilinx Employee
308 Views
Registered: ‎05-08-2012

Re: Still getting RTSTAT-2 violation after using "Fix Routes" Option

Hi @dcw15 

The FIXED_ROUTE constraints set the resources used for the logical net, but there looks to be contention for resources. This does not set the ordering of routing. The failure would indicate that other nets need the same resources. You could try pre-routing "route_design -nets", but I suspect that the another net might fail. Instead of restricting the resources availble to the debug nets, can the ILA logic be reduced? Debug logic can make designs more difficult to route and meet timing, due to the additional logic.


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Visitor dcw15
Visitor
290 Views
Registered: ‎02-28-2019

Re: Still getting RTSTAT-2 violation after using "Fix Routes" Option

Hi marc,

 

I really have put in the minimum amount of debug I need for this I think. I'll check with who I am helping with the build and see if anything can be dropped. There's <150 nets however and over 50% of the device is still free, so it doesn't seem like this should be much of an issue.

 

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Moderator
Moderator
220 Views
Registered: ‎01-16-2013

Re: Still getting RTSTAT-2 violation after using "Fix Routes" Option

@dcw15 

 

Any update on this thread?

 

--Syed

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Visitor dcw15
Visitor
164 Views
Registered: ‎02-28-2019

Re: Still getting RTSTAT-2 violation after using "Fix Routes" Option

Sorry for the slow reply - in the end the issue was although the line was easily accessable to see in HDL designer etc, from the source to output was only made up of parts of the chip which are not in the programmable logic section and as such couldn't be accessed with the debug. (Or i should say, this is the conclusion i came to and was replicable in similar circumstances)

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