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Participant vizziee
Participant
8,187 Views
Registered: ‎10-21-2009

Strange routing problem with DCM

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Hello,

 

I have a design targeted for Virtex5SXT95 device which compiles perfectly well. I wanted to test a submodule (specifically, inputs and outputs of a a simple dual-port BlockRam) and so I added ChipscopePro to that submodule. However, after addition of ChipscopePro, the design won't compile and give the following error:

 


 

 

ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block <Sub_module/DCM_instantiation> has CLK output pin <CLK180> with incomplete or incorrect connectivity. Routing from the <CLK180> pin to a BUFG, BUFGCTRL or PLL_ADV block type was not found. The DCM_ADV CLK output pins can only route to BUFG, BUFGCTRL or PLL_ADV block types.
ERROR:Pack:1642 - Errors in physical DRC.

 


 

 

This is strange considering when I remove the ChipscopePro from the module, the Map goes ahead without any error. Also, if I attach ChipscopePro to some other sub-module, I don't see this error. I also tried removing and deleting ILA and ICON modules from the hard disk and recreating them but I would always get the above error.

Also, the DCM block output pins are actually connected to BUFG and I had absolutely no problem with that block so far.

 

Has anyone faced a similar problem. Any help would be greatly appreciated.

 

Sincerely,

 

Kumar Vijay Mishra.

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Participant vizziee
Participant
10,689 Views
Registered: ‎10-21-2009

Re: Strange routing problem with DCM

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I solved the problem after some rigorous debugging. I was trying to capture the inputs and outputs of the dual-port RAM on the ChipscopePro. The dual-port RAM was set for common clocks for inputs and outputs, however the inputs were registered at a different clock. I wanted to observe both inputs and outputs on the same ILA so I had to specify one clock to ILA (I specified the output port clock). The compilation would run succesfully as long as the ILA data captured either the inputs alone or the outputs alone (irrespective of which clock I used). Whenever I would combine both of them for ILA data bus, I would get the errors mentioned before.

 

To resolve this, I changed the dual-port RAM setting to disable common clock feature and specified the two different clocks to the input and output. I did not get any errors therafter.

 

Sincerely,

 

Kumar Vijay Mishra.

View solution in original post

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6 Replies
Participant vizziee
Participant
8,180 Views
Registered: ‎10-21-2009

Re: Strange routing problem with DCM

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Some other information that may be useful here:

- I am using ISE 12.4 on Win XP 32-bit. I have also tried it on RHEL 5 64-bit and got the same error.

- The trigger for the ChipscopePro is same for the submodules.

 

Sincerely,

 

Kumar Vijay Mishra.

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Instructor
Instructor
8,165 Views
Registered: ‎08-14-2007

Re: Strange routing problem with DCM

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Did you route the clock signal (clk180) to the ila module?  If so did you route it to

a trigger / data input?  Theoretically you should only route a clock net to the clock

input of the ila module.  Also the ila clock input must be driven by a BUFG or BUFR

or similar clock buffer.

 

-- Gabor

-- Gabor
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Participant vizziee
Participant
8,162 Views
Registered: ‎10-21-2009

Re: Strange routing problem with DCM

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Tags (1)
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Instructor
Instructor
8,152 Views
Registered: ‎08-14-2007

Re: Strange routing problem with DCM

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Here's a possibility.  Maybe adding the extra clock signal for the ILA module has

broken the routing for your DCM_ADV.  Try adding something simple to the design

using the additional clock (but without adding the ChipScope).  For instance route

the clock to a single toggle flip-flop that drives an output pin.  See if that also causes

the error in the routing.

 

-- Gabor

-- Gabor
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Participant vizziee
Participant
8,150 Views
Registered: ‎10-21-2009

Re: Strange routing problem with DCM

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Hi gszakacs,

 

I have attempted that before. I added an additional block (a filter) to the design which uses the same clock and there wasn't any ChipscopePro in the design. There wasn't any routing problem and the design compiled without any errors.  In fact I have added ChipscopePro to that design as well and it compiled successfully.

 

Sincerely,

 

Kumar Vijay Mishra.

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Highlighted
Participant vizziee
Participant
10,690 Views
Registered: ‎10-21-2009

Re: Strange routing problem with DCM

Jump to solution

I solved the problem after some rigorous debugging. I was trying to capture the inputs and outputs of the dual-port RAM on the ChipscopePro. The dual-port RAM was set for common clocks for inputs and outputs, however the inputs were registered at a different clock. I wanted to observe both inputs and outputs on the same ILA so I had to specify one clock to ILA (I specified the output port clock). The compilation would run succesfully as long as the ILA data captured either the inputs alone or the outputs alone (irrespective of which clock I used). Whenever I would combine both of them for ILA data bus, I would get the errors mentioned before.

 

To resolve this, I changed the dual-port RAM setting to disable common clock feature and specified the two different clocks to the input and output. I did not get any errors therafter.

 

Sincerely,

 

Kumar Vijay Mishra.

View solution in original post

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