07-24-2016 09:35 PM
ERROR:PhysDesignRules:1709 - Incomplete connectivity. The pin <D2> of comp block <osc3/oc> is used and partially connected to network <current_j<4>>. All networks must have complete connectivity through out the comp hierarchy and the connectivity for this pin must be removed or completed.
This is on a Spartan6 XC6SLX9 TQG144.
FPGA editor view of offending slice:
It complains that there are inputs to LUTs connected, when those inputs are not used in the LUT equation. You might think that's silly, but it's required to implement the delay-LUTs described in this paper: http://www.aceslab.org/sites/default/files/ches-fpga-random.pdf (see "Fig. 11: Coarse and ﬁne PDLs implemented by a single 6-input LUT.")
I am using ISE 14.7, how do i disable this WRONG bitgen DRC check, since those smart fellows obviously managed to implement it and run it on a FPGA just fine (the way i even got it to generate this is manually instantiating LUTs and placing them, but instantiating them with AND formula first, so all nets are kept, then changing the formula in FPGA editor)
07-24-2016 09:58 PM
07-25-2016 05:47 AM
No, what I actually needed was the bitgen -d flag, or just unchecking "Run DRC" option in "Generate programming file" process options.
What i was actually looking for was a way to suppress ONLY THIS DRC, not all (and the environment variable you suggested would bypass DRC in Map, not BitGen/Place)
07-25-2016 06:11 AM
Check if the following Link helps:
07-25-2016 06:48 AM
How would that help ? Either the DRC does not run at all and i dont get any messages and the bitfile is created, or the DRC does run and makes ERRORs and the bitfile is not created. Suppressing messages wouldn't help.
07-26-2016 09:50 PM