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Anonymous
Not applicable
7,438 Views

Suppress "ERROR:PhysDesignRules:1709 - Incomplete connectivity." DRC check in bitgen ?

ERROR:PhysDesignRules:1709 - Incomplete connectivity. The pin <D2> of comp block
   <osc3/oc> is used and partially connected to network <current_j<4>>. All
   networks must have complete connectivity through out the comp hierarchy and
   the connectivity for this pin must be removed or completed.

This is on a Spartan6 XC6SLX9 TQG144.

FPGA editor view of offending slice: FPGA Editor Unused LUT Inputs

 

It complains that there are inputs to LUTs connected, when those inputs are not used in the LUT equation. You might think that's silly, but it's required to implement the delay-LUTs described in this paper: http://www.aceslab.org/sites/default/files/ches-fpga-random.pdf (see "Fig. 11: Coarse and fine PDLs implemented by a single 6-input LUT.")

 

I am using ISE 14.7, how do i disable this WRONG bitgen DRC check, since those smart fellows obviously managed to implement it and run it on a FPGA just fine (the way i even got it to generate this is manually instantiating LUTs and placing them, but instantiating them with AND formula first, so all nets are kept, then changing the formula in FPGA editor)

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Xilinx Employee
Xilinx Employee
7,427 Views
Registered: ‎10-24-2013

Re: Suppress "ERROR:PhysDesignRules:1709 - Incomplete connectivity." DRC check in bitgen ?

Hi @Anonymous

http://www.xilinx.com/support/answers/35506.html

http://www.xilinx.com/support/answers/35505.html

Thanks,Vijay
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Anonymous
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7,408 Views

Re: Suppress "ERROR:PhysDesignRules:1709 - Incomplete connectivity." DRC check in bitgen ?

No, what I actually needed was the bitgen -d flag, or just unchecking "Run DRC" option in "Generate programming file" process options.

 

What i was actually looking for was a way to suppress ONLY THIS DRC, not all (and the environment variable you suggested would bypass DRC in Map, not BitGen/Place)

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Moderator
Moderator
7,405 Views
Registered: ‎01-16-2013

Re: Suppress "ERROR:PhysDesignRules:1709 - Incomplete connectivity." DRC check in bitgen ?

@Anonymous,

 

Check if the following Link helps:

http://www.xilinx.com/itp/xilinx10/isehelp/ise_p_ds_using_message_filters.htm

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Anonymous
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7,403 Views

Re: Suppress "ERROR:PhysDesignRules:1709 - Incomplete connectivity." DRC check in bitgen ?

How would that help ? Either the DRC does not run at all and i dont get any messages and the bitfile is created, or the DRC does run and makes ERRORs and the bitfile is not created. Suppressing messages wouldn't help.

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Anonymous
Not applicable
7,336 Views

Re: Suppress "ERROR:PhysDesignRules:1709 - Incomplete connectivity." DRC check in bitgen ?

I converted my special design into a hard macro and instantiated it multiple times, however, now, during PAR, it's pin-swapping my LUTs ! And i have no idea how to LOCK_PINS=ALL on a hard macro inst (since that only works on a LUT inst) Help ?

 

2016-07-27_06-47-05.png

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