05-18-2018 12:22 AM
I am working with Tandem PROM for PCI_E Boot speed on vivado 18.1
I think everything is okay. example design & my user logic are okay.
but when I added the ILA for debugging, I got the this error(attached File "Tandem_PROM_Error1.png")
As you can see, Vivdao tool tell me the solution.
"set property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub/inst/BSCANID.uxsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]"
So I added this sentence on my .xdc file.
But I got a same error, this sentence made a warning message. (attached File "Tandem_PROM_Error2.png")
This problem make me crazy. please help me.
05-18-2018 09:46 AM
Take a look at the implementation log files. My expectation is that this constraint has been removed because it was not able to find the instance it applies to. The Debug flow inserts logic such as the BSCAN during opt_design, and since the constraint has been read in prior to this step, it would have been trimmed before the instance was added to the design. Instead of placing this constraint in your general .xdc file, place it in a separate .tcl file and reference it in a post-opt/pre-place step. Looking at the design run options in the project, you can see tcl.pre and tcl.post opportunities for inserting new constraints.
05-18-2018 09:27 PM
I really appreciate you help.
I made the new .tcl file and I added this .tcl file to [Settings -> Implementation -> tcl.pre* of Place Design]
This problem get solved. ^^
05-22-2018 03:33 AM
Thanks for the update. Glad to know the issue is now resolved. Can you please close this thread by marking the helpful post as "Accept as solution"
02-20-2019 04:39 PM