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Visitor uramashi2
Visitor
774 Views
Registered: ‎11-13-2017

Tandem PROM. Place & Route Error on vivado18.1. The board is KCU1525.

Hi guys.

 

I am working with Tandem PROM for PCI_E Boot speed on vivado 18.1

 

I think everything is okay. example design & my user logic are okay.

 

but when I added the ILA for debugging, I got the this error(attached File "Tandem_PROM_Error1.png")

 

As you can see, Vivdao tool tell me the solution.

 

"set property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells dbg_hub/inst/BSCANID.uxsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst]"

 

So I added this sentence on my .xdc file.

 

But I got a same error, this sentence made a warning message. (attached File "Tandem_PROM_Error2.png")

 

This problem make me crazy. please help me.

 

Thanks.

Tandem_PROM_Error1.png
Tandem_PROM_Error2.png
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4 Replies
Xilinx Employee
Xilinx Employee
745 Views
Registered: ‎11-17-2008

Re: Tandem PROM. Place & Route Error on vivado18.1. The board is KCU1525.

@uramashi2,

 

Take a look at the implementation log files.  My expectation is that this constraint has been removed because it was not able to find the instance it applies to.  The Debug flow inserts logic such as the BSCAN during opt_design, and since the constraint has been read in prior to this step, it would have been trimmed before the instance was added to the design.  Instead of placing this constraint in your general .xdc file, place it in a separate .tcl file and reference it in a post-opt/pre-place step.  Looking at the design run options in the project, you can see tcl.pre and tcl.post opportunities for inserting new constraints.

 

thanks,

david.

Visitor uramashi2
Visitor
725 Views
Registered: ‎11-13-2017

Re: Tandem PROM. Place & Route Error on vivado18.1. The board is KCU1525.

You're right.

 

I really appreciate you help.

 

I made the new .tcl file and I added this .tcl file to [Settings -> Implementation -> tcl.pre* of Place Design]

 

This problem get solved. ^^

 

Thanks you.

 

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Moderator
Moderator
680 Views
Registered: ‎01-16-2013

Re: Tandem PROM. Place & Route Error on vivado18.1. The board is KCU1525.

@uramashi2,

 

Thanks for the update. Glad to know the issue is now resolved. Can you please close this thread by marking the helpful post as "Accept as solution"

 

--Syed

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Observer agdhun
Observer
143 Views
Registered: ‎05-14-2018

Re: Tandem PROM. Place & Route Error on vivado18.1. The board is KCU1525.

made the new .xdc can set to used in place_design, so not be loaded in implement, only loaded in place design
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