07-22-2013 06:22 AM
07-22-2013 07:18 AM
What parts are you comparing? What is the nature of the design (where did the source come from)? Trying to place us in a smaller part is quite unfair...
Learning how to use the tools is something that is required.
The defaults used by different vendors are substantially different.
Xilinx has always taken the view that if the tiools succeed, you will succeed. Others have had a different view: the tools succeed, and then you have to figure out why it doesn't work (usually). Quite clever. By that time, you are so deep into the project, there is no turning back.
By setting the bar higher, the designs run more smoothly, customers become more loyal.
So, do not tell us about the competitor (we are not stupid, and we know quite well what their tools purport to do.
Tell us about what strategies you have tried in our tools (area optimization, performance optimization, etc.).
Also, you might try Vivado, which has significantly improved the synthesis, place and routing (not just better than ISE, but better than everyone).
07-23-2013 02:29 PM
Routing congestion/failure to route is quite common in V6 designs with large datapaths, so I'd recommend floorplanning your design to avoid creating overlapping paths. By itself the tools will run into trouble as ISE's PNR algorithms use randomness~
Vivado is much, much better, but you still can run into routing issues requiring a good floorplan - and unfortunately unless things have changed recently, you cannot use Vivado for V6 designs (only V7 and newer designs).
We posted some routing estimates for floorplanning for reference in another thread: http://forums.xilinx.com/t5/7-Series-FPGAs/interconnect-resources-in-Virtex-7/td-p/328037
07-24-2013 11:23 AM
I'm designing a project of image-processing (about 5M gates,using Virtex-6 device ) , when I use ISE 13.3 or ISE 14.2 to achieve PAR , it always failed and issued the warning of congested design . And so is using some optimized strategy in PlanAhead. But when I transplant my project to Altera device (Stratix-IV) , using QuartusII to achieve PAR , it is done smothly, and successfully runned at board. So what is the matter about ISE? Is there some setting we should do before PAR? Or it is the weakness of ISE when doing some congested design?
Since you haven't told us WHICH V6 device you are using and WHICH Stratix device you are using -- and by that I mean exact part numbers, please -- one can't do a fair comparison.
Because if the V6 device you target is 90% full and the S4 device you choose is only 60% full, naturally one might expect the latter to route and the former to possibly not.
07-25-2013 12:07 AM
Its possible that there could be congeston issues for larger designs in V-6.
Some suggestions to address the congestion issue are:
- Try SmartXplorer with and without the congestion reduction option "-cr"
- Examine the partially routed design in FPGA Editor to see where the congestion (unrouted nets) is
- Also in FPGA Editor, set the list window to "all nets", sort by fanout. Select the highest fanout nets and see if they correspond to the areas of congestion.
- Try some fanout reduction, floorplanning or restructuring of the design for the congested areas.
-Use “Vertical/Horizontal Routing Congestion per CLB" feature in PlanAhead Metrics window for your design to further evaluate this.
There is also a video available: How do I Resolve Routing Congestion?
Another video that may be useful is: What Design Techniques Help Avoid Routing Congestion?
Also, for Virtex-6 devices, a White Paper has been published to help with routing designs: