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Explorer
224 Views
Registered: ‎01-15-2019

[Timing Closure] -> long route (~75% of total path delay) -> how to solve/constrain?

Hi All,

I have a problem with a Timing Closure...

Clock Period: 6.4ns

Data Path Delay (post P&R): 6.948ns (logic 1.899ns (27.332%) route 5.049ns (72.668%))

Logic Levels: 18 (CARRY4=5 LUT2=1 LUT6=12)

As you could see, most of the delay goes to the route (~72%) and leave for the logic delay just ~1.5ns.

So, what's the problem and how to fix it? The target device is Zynq 7045 and has a lot of resources (occupied just by ~25% by the logic).

Why the tool (Vivado) goes so long for the route?

Note: CDC is clean, no clock domain crossing violations...

Thank you!

 

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1 Reply
203 Views
Registered: ‎06-21-2017

Re: [Timing Closure] -> long route (~75% of total path delay) -> how to solve/constrain?

18 levels of logic is a lot for a design running with a fast clock.  You should add more pipeline registers to your design.  This will allow the tools to break up long paths.