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khyu
Contributor
Contributor
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Registered: ‎10-28-2018

Timing critical module keep last implementation

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 I have the critical design USB3 that run at 125Mhz.

The FPGA timing is very critical .

If I have some little change , for example 

TOPA--USB3A  => TOPB--USB3B

Critical Timing get worse and unstable

Can I keep USB3A  implementation layout and only modified part USB3A-USB3B is placed and routed?

 

 

 

 

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syedz
Moderator
Moderator
430 Views
Registered: ‎01-16-2013

@khyu 

 

You can try Incremental implementation with Vivado. Check page 101 in below user guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug904-vivado-implementation.pdf 

 

--Syed

---------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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syedz
Moderator
Moderator
431 Views
Registered: ‎01-16-2013

@khyu 

 

You can try Incremental implementation with Vivado. Check page 101 in below user guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug904-vivado-implementation.pdf 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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