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Scholar embedded
Scholar
3,488 Views
Registered: ‎06-09-2011

Tri mode Ethernet MAC problem in Vivado 2014

Hi all,

I am using a tri mode EMAC for a Kintex-7 in Vivado. I have already worked with this core in ISE 14.7. I receive a "Critical Warning" when starting implementation and consequently errors during implementation. Below picture shows the critical warning:

Critical Warning.jpg

 

I tried to comment this line in  the file -MyEth.xdc. But, it is not writable and I couldn't change this file. I looked further in core features and didn't realize how I can customize the core in order to prevent it from generating and inserting those lines into xdc file?! 

I would appreciate any comment.

Hossein

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2 Replies
Moderator
Moderator
3,479 Views
Registered: ‎01-16-2013

Re: Tri mode Ethernet MAC problem in Vivado 2014

@embedded,

 

Constraint in IP are scoped and it is expected that you connect these pins directly to top level ports.

 

In case of scoped constraints the get_ports returns top level ports if the IP Ports are connected directly to top level ports. If the ip ports are not connected to top level ports directly then get_ports is converted to get_ pins.

Please check page 40 in below User guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug903-vivado-using-constraints.pdf

 

--Syed

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Scholar embedded
Scholar
3,464 Views
Registered: ‎06-09-2011

Re: Tri mode Ethernet MAC problem in Vivado 2014

Hi,

Thanks for your answer. It seems that this core - here in Vivado - is wrapped with IOBs and must be connected directly to the top level entity ports. I have only observing one issue now. Some GMII_TXD IOs fail in timing at the final stage of bit file generation?! I don't see how I can manage with this problem? I am new to Vivado and need more help to find where and how exactly I can give adequate timing constraints?

 

Thanks,

Hossein

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