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Visitor mingming.li
Visitor
281 Views
Registered: ‎04-18-2019

Two questions for tandem PCIe floorplan.

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After reading <UltraScale Devices Gen3 Block for PCIe v4.4>(PG156 April 4, 2018)there are two descriptions for the floorplan to tandem.

PAGE 91: "Even though the Tandem with Field Updates approach utilizes Partial Reconfiguration, a PR
license is not required if the design structure and floorplan are not modified from the
sample generated with the IP."

PAGE 91: "First, for both variations, the floorplan is established as part of the IP creation and should
not be modified, but Tandem with Field Updates creates two sets of Pblocks instead of one." 

So, my first question is if the default floorplan can be modified?

The second question is if the default floorplan can be modified, What are the restrictions on modifying it?

 

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Xilinx Employee
Xilinx Employee
255 Views
Registered: ‎11-17-2008

Re: Two questions for tandem PCIe floorplan.

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The floorplan can be modified -- it is after all just a set of X-Y coordinates, but we recommend that users do not modify the automatically generated floorplan for a couple reasons:

1. We test in software and hardware the supplied floorplans and IP to ensure everything (enumeration, stage 2 loading, design behavior, PR if selected, etc.) functions as expected.  Now we expect the Tandem and PR parts of the solution to function well by design, but we really want this to be as pushbutton as possible out of the box, and changing the floorplan disrupts this goal.

2. To modify the floorplan requires experience with the PR solution, as the floorplan aligns to fundamental PR boundaries.  Basically this means shifting the edge two columns at a time to the left, but this can have greater repercussions as you start hitting resource types beyond CLB and BRAM.  There are more non-trivial things to consider if this happens.

3. Changing the floorplan implies that you want to put more logic in the stage 1 region, and that has other requirements of isolation and connectivity.  We take care of this for you with the Tandem version of the PCIe IP, but anything else added must also play by these rules, being able to independently exist decoupled from the rest of the design until stage 2 is loaded.  See the "OBUFT" comments in the PCIe Product Guides to see an example of this, as you add more IO to bank 65.  Anything in stage 1 must be decoupled (see the PR Decoupler for an example) so it can safely exist alone, and fit inside that box.

Basically, we do not have complete hardened PCIe IP in these devices (7 series through UltraScale+) which is great for flexibility, but for solutions like Tandem, we put up cones to keep users in a safe working environment.  You are asking to move the cones which is possible, but you need to understand the ramifications of this request.

thanks,

david.

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Xilinx Employee
Xilinx Employee
256 Views
Registered: ‎11-17-2008

Re: Two questions for tandem PCIe floorplan.

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The floorplan can be modified -- it is after all just a set of X-Y coordinates, but we recommend that users do not modify the automatically generated floorplan for a couple reasons:

1. We test in software and hardware the supplied floorplans and IP to ensure everything (enumeration, stage 2 loading, design behavior, PR if selected, etc.) functions as expected.  Now we expect the Tandem and PR parts of the solution to function well by design, but we really want this to be as pushbutton as possible out of the box, and changing the floorplan disrupts this goal.

2. To modify the floorplan requires experience with the PR solution, as the floorplan aligns to fundamental PR boundaries.  Basically this means shifting the edge two columns at a time to the left, but this can have greater repercussions as you start hitting resource types beyond CLB and BRAM.  There are more non-trivial things to consider if this happens.

3. Changing the floorplan implies that you want to put more logic in the stage 1 region, and that has other requirements of isolation and connectivity.  We take care of this for you with the Tandem version of the PCIe IP, but anything else added must also play by these rules, being able to independently exist decoupled from the rest of the design until stage 2 is loaded.  See the "OBUFT" comments in the PCIe Product Guides to see an example of this, as you add more IO to bank 65.  Anything in stage 1 must be decoupled (see the PR Decoupler for an example) so it can safely exist alone, and fit inside that box.

Basically, we do not have complete hardened PCIe IP in these devices (7 series through UltraScale+) which is great for flexibility, but for solutions like Tandem, we put up cones to keep users in a safe working environment.  You are asking to move the cones which is possible, but you need to understand the ramifications of this request.

thanks,

david.

Visitor mingming.li
Visitor
212 Views
Registered: ‎04-18-2019

Re: Two questions for tandem PCIe floorplan.

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Thanks for your kindly replay.  Our product is a PXIe module. We need access some registers over PCIe bar 0 before the stage 2 image was loaded. I removed all the logic for accessing these registers into stage 1. But the registers cant be accessed until stage 2 was loaded. So, if the PCIe bar can work before the stage2 was loaded? 

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